Bosch Appliances TTCAN user manual Transmission Request Registers, New Data Registers

Page 28

TTCAN

User’s Manual

Revision 1.6

3.4.2 Transmission Request Registers

 

 

 

 

 

 

 

 

 

Transmission Request 1 Register

15 14 13 12 11 10 9 8

7

6 5 4 3 2 1 0

 

 

(addresses 0x81 & 0x80)

 

 

 

 

 

TxRqst16-9

 

TxRqst8-1

 

 

 

 

 

 

 

 

Transmission Request 2 Register

TxRqst32-25

 

TxRqst24-17

 

 

(addresses 0x83 & 0x82)

 

 

 

 

 

r

 

r

 

 

 

 

 

 

 

 

 

 

 

TxRqst32-1Transmission Request Bits (of all Message Objects)

one The transmission of this Message Object is requested and is not yet done. zero This Message Object is not waiting for transmission.

These registers hold the TxRqst bits of the 32 Message Objects. By reading out the TxRqst bits, the CPU can check for which Message Object a Transmission Request is pending. The TxRqst bit of a specific Message Object can be set/reset by the CPU via the IFx Message Interface Registers or (when not in time triggered mode) by the Message Handler after reception of a Remote Frame or after a successful transmission.

3.4.3 New Data Registers

New Data 1 Register

15 14 13 12 11 10 9 8

7

6 5 4 3 2 1 0

(addresses 0x91 & 0x90)

 

 

 

NewDat16-9

 

NewDat8-1

 

 

 

 

New Data 2 Register

NewDat32-25

 

NewDat24-17

(addresses 0x93 & 0x92)

 

 

 

r

 

r

 

 

 

 

 

 

NewDat32-1New Data Bits (of all Message Objects)

one The Message Handler or the CPU has written new data into the data por- tion of this Message Object.

zero No new data has been written into the data portion of this Message Object by the Message Handler since last time this flag was cleared by the CPU.

MsgLstThese registers hold the NewDat bits of the 32 Message Objects. By reading out the NewDat bits, the CPU can check for which Message Object the data portion was updated. The NewDat bit of a specific Message Object can be set/reset by the CPU via the IFx Message Interface Registers or by the Message Handler after reception of a Data Frame or after a successful transmission.

3.4.4 Interrupt Pending Registers

manual_about.fm

Interrupt Pending 1 Register

15 14 13 12 11 10 9 8

7

6 5 4 3 2 1 0

(addresses 0xA1 & 0xA0)

 

 

 

IntPnd16-9

 

IntPnd8-1

 

 

 

 

Interrupt Pending 2 Register

IntPnd32-25

 

IntPnd24-17

(addresses 0xA3 & 0xA2)

 

 

 

r

 

r

 

 

 

 

 

 

IntPnd32-1Interrupt Pending Bits (of all Message Objects)

one This message object is the source of an interrupt. zero This message object is not the source of an interrupt.

These registers hold the IntPnd bits of the 32 Message Objects. By reading out the IntPnd bits, the CPU can check for which Message Object an interrupt is pending. The IntPnd bit of a specific Message Object can be set/reset by the CPU via the IFx Message Interface Registers or by the Message Handler after reception or after a successful transmission of a frame. This will also affect the value of IntId in the Interrupt Register.

BOSCH

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11.11.02

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Contents User’s Manual Robert Bosch GmbHCopyright Notice and Proprietary Information Change Control Functional Overview 2.2. Block Diagram Operating ModesConventions Scope References Terms and Abbreviations Can Application Ttcan Configuration Ttcan Schedule InitialisationTtcan Message Handling List of FiguresChange Control Current Status Change HistoryConventions Helvetica boldTerm Meaning Functional Overview Cpuifc TtcanOperating Modes Software Initialisation Can Message TransferTest Mode Disabled Automatic RetransmissionTest Register addresses 0x0B & 0x0A Ttcan =1 Loop Back Mode Loop Back combined with Silent ModeNo Message RAM Mode Software control of Pin CantxAddress Name Reset Value Hardware Reset Description Ttcan Register SummaryCCE DAREIE SIENo Error Status Register addresses 0x03Status Interrupts Error Counter addresses 0x05Bit Timing Register addresses 0x07 BRP Extension Register addresses 0x0D & 0x0C Direction = Write IFx Command Mask RegistersArb IFx Command Request Registers Direction = ReadControl ClrIntPndBusy Message NumberIFx Message Buffer Registers IFx Mask RegistersIFx Data a and Data B Registers IFx Message Control RegistersMessage Object in the Message Memory ID28-0 Msk28-0Xtd Dir26/77 11.11.02 Message Handler Registers Interrupt Register addresses 0x09New Data Registers Transmission Request RegistersInterrupt Pending Registers Message Valid 1 Register 2 IF1 Data B1 and B2 Registers for Trigger Memory AccessTrigger Number TT Operation Mode Register addresses 0x29 TypeTimeMark At CycleCount mod MPr2-0Rdlc EecsTEW TT Interrupt Enable Register addresses 0x31 CCMBark AppWdLCEL GTEGTW SWERTO TT Cycle Count Register addresses 0x3D & 0x3C TT Error Level Register addresses 0x3F & 0x3ETUR Numerator Configuration Low Register addresses 0x57 TUR Numerator Actual Registers addresses 0x5B & 0x5A TUR Denominator Configuration Register addresses 0x59TT StopWatch Register addresses 0x61 QCS QgtpEcal EgtfTMC DETECS SWSEPE TMG40/77 11.11.02 Internal can Message Handling Data Transfer Between IFx Registers and Message RAMTransmission of Messages in Event Driven can Communication StartAcceptance Filtering of Received Messages Reception of Data FrameReception of Remote Frame Storing Received Messages in Fifo BuffersReceive / Transmit Priority Configuration of the ModuleSync PropSeg PhaseSeg1 PhaseSeg2 1 Configuration of the Bit TimingBit Time and Bit Rate Canclk input Nominal can Bit TimePropagation Time Segment BRPPhase Buffer Segments and Synchronisation Synchronisation on late and early Edges Filtering of Short Dominant Spikes Oscillator Tolerance Range 1.5 Configuration of the can Protocol ControllerCalculation of the Bit Timing Parameters Example for Bit Timing at high Baudrate Example for Bit Timing at low Baudrate 2 Configuration of the Message Memory2.1 Configuration of a Transmit Object for Data Frames 2.2 Configuration of a Single Receive Object for Data Frames2.3 Configuration of a Fifo Buffer Can Communication Handling of InterruptsUpdating a Transmit Object Changing a Transmit Object Reading Received MessagesRequesting New Data for a Receive Object Reading from a Fifo BufferCPU Handling of a Fifo Buffer Interrupt Driven Ttcan Configuration Ttcan Timing510 125000 32.5 100/12 529/17 TURMessage Scheduling Trigger Memory 63/77 11.11.02 Reference Message Message ObjectsPeriodic Transmit Message Time Slaves Event Driven Transmit MessagePotential Time Masters Ttcan Message Handling Message Reception Message TransmissionPeriodic Messages Event Driven MessagesTtcan Gap Control StopwatchCycle Time and Global Time Synchronisation Ttcan Interrupt and Error Handling Previous RefMarkConfiguration Example Register Remark Rdlc & TEW & CCMType & Msg & CycleCode RTO , TM , L2 , TTMode3 74/77 11.11.02 Interface GenericCustomer Interface Timing of the Wait output signal Canclk CanwaitbBusy = ‘1’ Busy = ‘0’ Interrupt TimingEOF
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