Bosch Appliances TTCAN user manual Tur, 510 125000 32.5 100/12 529/17, Message Scheduling

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TTCAN

User’s Manual

Revision 1.6

manual_about.fm

TUR

8

10

24

50

510

125000

32.5

100/12

529/17

 

 

 

 

 

 

 

 

 

 

NumCfg

0x1FFF8

0x1FFFE

0x1FFF8

0x1FFEA

0x1FFFE

0x1E848

0x1FFE0

0x19000

0x10880

 

 

 

 

 

 

 

 

 

 

DenomCfg

0x3FFF

0x3333

0x1555

0x0A3D

0x0101

0x0001

0x0FC0

0x3000

0x0880

 

 

 

 

 

 

 

 

 

 

Figure 18: TUR configuration examples

The TTCAN module provides a watchdog to verity the function of the application program. The host has to serve this watchdog regularly, else all CAN bus activity is stopped. The Application Watchdog Limit AppWdL (range 0x00 to 0xFF) specifies the maximum number of 256•NTUs between two times the watchdog is served. The Application Watchdog Limit may be written during Configuration Mode, its default value is 0x01. The Watchdog is served by reading the (high byte of the) Application Watchdog Limit register. The MSB of this register shows whether the watchdog has been served in time.

After hardware reset, the length of the NTU is 16 System Clock Periods, but the Local Time and the Watchdog Timer are not started before either the Init bit in the CAN Control register is reset or the ELT bit in the Clock Control register is set. ELT may not be set before the NTU is configured, setting ELT to ‘1’ also locks the write access to the TUR Denominator Configuration Register.

For software development, the watchdog may be disabled by setting the WdOff bit in the Test register and setting AppWdL to 0x00, see chapter 2.3.4.2.

5.1.2 Message Scheduling

TM in the Operation Mode register controls whether the TTCAN module operates as a potential Time Master or exclusively as a Time Slave. If it is a potential Time Master, MPr[2…0] defines its master priority, 0 giving the highest and 7 giving the lowest priority. There may not be two nodes in the network using the same master priority, since the master priority is identical to the three LSBs of the Reference Message Identifier. MPr is not relevant for Time Slaves.

The Initial Reference Trigger Offset Init_Ref_Offset is a 7-bit-value that defines (in NTUs) how long a backup Time Master waits before it starts the transmission of a Reference Message when a Reference Message is expected but the bus remains idle. The recommended value for Init_Ref_Offset is MPr multiplied with a factor, the factor depending on the expected clock drift between the potential Time Masters in the network. The sequential order of the backup Time Masters, when one of them starts the Reference Message in case the current Time Master fails, should correspond to their master priority, even with maximum clock drift.

L2 decides whether the node operates in TTCAN Level 1 or in TTCAN Level 2. In one network, all potential Time Masters have to operate in the same level. Time Slaves may operate on Level 1 in a Level 2 network, but not vice versa.

EECS enables the external clock synchronisation, allowing the application program of the current Time Master to update the TUR configuration during Time Triggered Operation, to adapt the clock speed and (in Level 2 only) the Global Clock phase to an external reference.

The configuration of the TTCAN Operation Mode TTMode is the last step in the setup, since the configuration registers are writable in “Configuration Mode” only. In the TTMode “Event driven CAN Communication”, the TTCAN module operates according to ISO 11898-1, without Time Triggers. In the TTMode “Strictly Time Triggered Operation”, the TTCAN module

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Contents Robert Bosch GmbH User’s ManualCopyright Notice and Proprietary Information Change Control Functional Overview 2.2. Block Diagram Operating ModesConventions Scope References Terms and Abbreviations Can Application Ttcan Schedule Initialisation Ttcan ConfigurationTtcan Message Handling List of FiguresChange History Change Control Current StatusConventions Helvetica boldTerm Meaning Functional Overview Ttcan CpuifcCan Message Transfer Operating Modes Software InitialisationTest Mode Disabled Automatic RetransmissionTest Register addresses 0x0B & 0x0A Ttcan =1 Loop Back combined with Silent Mode Loop Back ModeSoftware control of Pin Cantx No Message RAM ModeAddress Name Reset Value Ttcan Register Summary Hardware Reset DescriptionDAR CCEEIE SIEStatus Register addresses 0x03 No ErrorStatus Interrupts Error Counter addresses 0x05Bit Timing Register addresses 0x07 BRP Extension Register addresses 0x0D & 0x0C Direction = Write IFx Command Mask RegistersArb Direction = Read IFx Command Request RegistersControl ClrIntPndMessage Number BusyIFx Message Buffer Registers IFx Mask RegistersIFx Data a and Data B Registers IFx Message Control RegistersMessage Object in the Message Memory Msk28-0 ID28-0Xtd Dir26/77 11.11.02 Interrupt Register addresses 0x09 Message Handler RegistersNew Data Registers Transmission Request RegistersInterrupt Pending Registers Message Valid 1 Register 2 IF1 Data B1 and B2 Registers for Trigger Memory AccessTrigger Number Type TT Operation Mode Register addresses 0x29TimeMark At CycleCount mod MPr2-0Rdlc EecsTEW CCM TT Interrupt Enable Register addresses 0x31Bark AppWdLGTE CELGTW SWERTO TT Cycle Count Register addresses 0x3D & 0x3C TT Error Level Register addresses 0x3F & 0x3ETUR Numerator Configuration Low Register addresses 0x57 TUR Numerator Actual Registers addresses 0x5B & 0x5A TUR Denominator Configuration Register addresses 0x59TT StopWatch Register addresses 0x61 Qgtp QCSEcal EgtfDET TMCECS SWSTMG EPE40/77 11.11.02 Data Transfer Between IFx Registers and Message RAM Internal can Message HandlingStart Transmission of Messages in Event Driven can CommunicationReception of Data Frame Acceptance Filtering of Received MessagesReception of Remote Frame Storing Received Messages in Fifo BuffersConfiguration of the Module Receive / Transmit Priority1 Configuration of the Bit Timing Sync PropSeg PhaseSeg1 PhaseSeg2Bit Time and Bit Rate Canclk input Nominal can Bit TimeBRP Propagation Time SegmentPhase Buffer Segments and Synchronisation Synchronisation on late and early Edges Filtering of Short Dominant Spikes 1.5 Configuration of the can Protocol Controller Oscillator Tolerance RangeCalculation of the Bit Timing Parameters Example for Bit Timing at high Baudrate 2 Configuration of the Message Memory Example for Bit Timing at low Baudrate2.2 Configuration of a Single Receive Object for Data Frames 2.1 Configuration of a Transmit Object for Data Frames2.3 Configuration of a Fifo Buffer Handling of Interrupts Can CommunicationUpdating a Transmit Object Reading Received Messages Changing a Transmit ObjectRequesting New Data for a Receive Object Reading from a Fifo BufferCPU Handling of a Fifo Buffer Interrupt Driven Ttcan Timing Ttcan Configuration510 125000 32.5 100/12 529/17 TURMessage Scheduling Trigger Memory 63/77 11.11.02 Reference Message Message ObjectsPeriodic Transmit Message Time Slaves Event Driven Transmit MessagePotential Time Masters Message Transmission Ttcan Message Handling Message ReceptionPeriodic Messages Event Driven MessagesStopwatch Ttcan Gap ControlCycle Time and Global Time Synchronisation Previous RefMark Ttcan Interrupt and Error HandlingConfiguration Example Rdlc & TEW & CCM Register RemarkType & Msg & CycleCode RTO , TM , L2 , TTMode3 74/77 11.11.02 Interface GenericCustomer Interface Canclk Canwaitb Timing of the Wait output signalBusy = ‘1’ Busy = ‘0’ Interrupt TimingEOF
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