Bosch Appliances TTCAN user manual Cce, Dar, Eie, Sie

Page 17

TTCAN

User’s Manual

Revision 1.6

manual_about.fm

3.2 CAN Protocol Related Registers

These registers are related to the CAN protocol controller in the CAN Core. They control the operating modes and the configuration of the CAN bit timing and provide status information.

3.2.1 CAN Control Register (addresses 0x01 & 0x00)

15

14

13

12

 

11

 

10

 

9

 

8

7

6

5

4

 

3

 

2

 

1

0

 

res

res

res

res

 

res

 

res

 

res

 

res

Test

CCE

DAR

res

 

EIE

 

SIE

 

IE

Init

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

r

r

r

r

r

r

r

r

rw

rw

rw

r

rw

rw

rw

rw

Test

 

Test Mode Enable

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

one

Test Mode.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

zero

Normal Operation.

 

 

 

 

 

 

 

 

 

 

 

 

CCE

 

Configuration Change Enable

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

one

The CPU has write access to the configuration registers (while Init = one).

 

 

 

zero

The CPU has no write access to the configuration registers.

 

 

DAR

 

Disable Automatic Retransmission

 

 

 

 

 

 

 

 

 

 

 

 

 

 

one

Automatic Retransmission disabled.

 

 

 

 

 

 

 

 

 

 

 

 

zero

Automatic Retransmission of not successful messages enabled.

 

 

EIE

 

Error Interrupt Enable

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

one

Enabled - A change in the bits BOff or EWarn in the Status Register will

 

 

 

 

generate an interrupt.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

zero

Disabled - No Error Status Interrupt will be generated.

 

 

 

 

SIE

 

Status Change Interrupt Enable

 

 

 

 

 

 

 

 

 

 

 

 

 

 

one

Enabled - An interrupt will be generated when a message transfer is suc-

 

 

 

 

cessfully completed or a CAN bus error is detected.

 

 

 

 

 

 

 

 

 

zero

Disabled - No Status Change Interrupt will be generated.

 

 

 

 

IE

 

Module Interrupt Enable

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

one

Enabled - Interrupts will set IRQ_B to LOW. IRQ_B remains LOW until all

 

 

 

 

pending interrupts are processed.

 

 

 

 

 

 

 

 

 

 

 

 

zero

Disabled - Module Interrupt IRQ_B is always HIGH.

 

 

 

 

 

 

Init

 

Initialization

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

one

Initialization is started.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

zero

Normal Operation.

 

 

 

 

 

 

 

 

 

 

 

 

The configuration registers controlled by CCE are the Bit Timing Register, the BRP Extension Register, and the TT Operation Mode Register.

Note : The Bus_Off recovery sequence (see CAN Specification Rev. 2.0) cannot be shortened by set- ting or resetting Init. If the device goes Bus_Off, it will set Init of its own accord, stopping all bus activities. Once Init has been cleared by the CPU, the device will then wait for 129 occurrences of Bus Idle (129 * 11 consecutive recessive bits) before resuming normal operations. At the end of the Bus_Off recovery sequence, the Error Management Counters will be reset.

During the waiting time after the resetting of Init, each time a sequence of 11 recessive bits has been monitored, a Bit0Error code is written to the Status Register, enabling the CPU to readily check up whether the CAN bus is stuck at dominant or continuously disturbed and to monitor the proceeding of the Bus_Off recovery sequence.

BOSCH

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11.11.02

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Contents Robert Bosch GmbH User’s ManualCopyright Notice and Proprietary Information Conventions Scope References Terms and Abbreviations Functional Overview 2.2. Block Diagram Operating ModesChange Control Can Application Ttcan Schedule Initialisation Ttcan ConfigurationTtcan Message Handling List of FiguresChange History Change Control Current StatusConventions Helvetica boldTerm Meaning Functional Overview Ttcan CpuifcCan Message Transfer Operating Modes Software InitialisationTest Register addresses 0x0B & 0x0A Disabled Automatic RetransmissionTest Mode Ttcan =1 Loop Back combined with Silent Mode Loop Back ModeSoftware control of Pin Cantx No Message RAM ModeAddress Name Reset Value Ttcan Register Summary Hardware Reset DescriptionDAR CCEEIE SIEStatus Register addresses 0x03 No ErrorBit Timing Register addresses 0x07 Error Counter addresses 0x05Status Interrupts BRP Extension Register addresses 0x0D & 0x0C Arb IFx Command Mask RegistersDirection = Write Direction = Read IFx Command Request RegistersControl ClrIntPndMessage Number BusyIFx Message Buffer Registers IFx Mask RegistersMessage Object in the Message Memory IFx Message Control RegistersIFx Data a and Data B Registers Msk28-0 ID28-0Xtd Dir26/77 11.11.02 Interrupt Register addresses 0x09 Message Handler RegistersInterrupt Pending Registers Transmission Request RegistersNew Data Registers Trigger Number 2 IF1 Data B1 and B2 Registers for Trigger Memory AccessMessage Valid 1 Register Type TT Operation Mode Register addresses 0x29TimeMark At CycleCount mod MPr2-0TEW EecsRdlc CCM TT Interrupt Enable Register addresses 0x31Bark AppWdLGTE CELGTW SWERTO TUR Numerator Configuration Low Register addresses 0x57 TT Error Level Register addresses 0x3F & 0x3ETT Cycle Count Register addresses 0x3D & 0x3C TT StopWatch Register addresses 0x61 TUR Denominator Configuration Register addresses 0x59TUR Numerator Actual Registers addresses 0x5B & 0x5A Qgtp QCSEcal EgtfDET TMCECS SWSTMG EPE40/77 11.11.02 Data Transfer Between IFx Registers and Message RAM Internal can Message HandlingStart Transmission of Messages in Event Driven can CommunicationReception of Data Frame Acceptance Filtering of Received MessagesReception of Remote Frame Storing Received Messages in Fifo BuffersConfiguration of the Module Receive / Transmit Priority1 Configuration of the Bit Timing Sync PropSeg PhaseSeg1 PhaseSeg2Bit Time and Bit Rate Canclk input Nominal can Bit TimeBRP Propagation Time SegmentPhase Buffer Segments and Synchronisation Synchronisation on late and early Edges Filtering of Short Dominant Spikes 1.5 Configuration of the can Protocol Controller Oscillator Tolerance RangeCalculation of the Bit Timing Parameters Example for Bit Timing at high Baudrate 2 Configuration of the Message Memory Example for Bit Timing at low Baudrate2.2 Configuration of a Single Receive Object for Data Frames 2.1 Configuration of a Transmit Object for Data Frames2.3 Configuration of a Fifo Buffer Handling of Interrupts Can CommunicationUpdating a Transmit Object Reading Received Messages Changing a Transmit ObjectRequesting New Data for a Receive Object Reading from a Fifo BufferCPU Handling of a Fifo Buffer Interrupt Driven Ttcan Timing Ttcan ConfigurationMessage Scheduling TUR510 125000 32.5 100/12 529/17 Trigger Memory 63/77 11.11.02 Periodic Transmit Message Message ObjectsReference Message Potential Time Masters Event Driven Transmit MessageTime Slaves Message Transmission Ttcan Message Handling Message ReceptionPeriodic Messages Event Driven MessagesStopwatch Ttcan Gap ControlCycle Time and Global Time Synchronisation Previous RefMark Ttcan Interrupt and Error HandlingConfiguration Example Rdlc & TEW & CCM Register RemarkType & Msg & CycleCode RTO , TM , L2 , TTMode3 74/77 11.11.02 Customer Interface GenericInterface Canclk Canwaitb Timing of the Wait output signalBusy = ‘1’ Busy = ‘0’ Interrupt TimingEOF
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