Bosch Appliances TTCAN user manual Status Interrupts, Error Counter addresses 0x05

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TTCAN

User’s Manual

Revision 1.6

manual_about.fm

The LEC ﬁeld holds a code which indicates the type of the last error to occur on the CAN bus. This ﬁeld will be cleared to ‘0’ when a message has been transferred (reception or transmis- sion) without error. The unused code ‘7’ may be written by the CPU to check for updates.

3.2.2.1 Status Interrupts

A Status Interrupt is generated by bits BOff and EWarn (Error Interrupt, EIE) or by RxOk, TxOk, and LEC (Status Change Interrupt, SIE) assumed that the corresponding enable bits in the CAN Control Register are set. A change of bit EPass or a CPU write to RxOk, TxOk, or LEC will never generate a Status Interrupt.

When SIE is set, a Status Interrupt will be generated at each CAN bus error and at each valid CAN message, independent of the Message RAM conﬁguration.

Reading the Status Register will clear the Status Interrupt value (8000h) in the Interrupt Register, if it is pending.

3.2.3 Error Counter (addresses 0x05 & 0x04)

15		14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	RP				REC6-0							TEC7-0

	r				r								r
RP			Receive Error Passive
			one	The Receive Error Counter has reached the error passive level as deﬁned
				in the CAN Speciﬁcation.
			zero	The Receive Error Counter is below the error passive level.

REC6-0Receive Error Counter

Actual state of the Receive Error Counter. Values between 0 and 127.

TEC7-0Transmit Error Counter

Actual state of the Transmit Error Counter. Values between 0 and 255.

3.2.4 Bit Timing Register (addresses 0x07 & 0x06)

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
res		TSeg2			TSeg1				SJW				BRP

r		rw				rw			rw				rw

TSeg1 The time segment before the sample point

0x01-0x0Fvalid values for TSeg1 are [1 … 15]. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used.

TSeg2 The time segment after the sample point

0x0-0x7valid values for TSeg2 are [0 … 7]. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used.

SJW (Re)Synchronisation Jump Width

0x0-0x3Valid programmed values are 0-3. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used.

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Contents Robert Bosch GmbH User’s ManualCopyright Notice and Proprietary Information Change Control Functional Overview 2.2. Block Diagram Operating ModesConventions Scope References Terms and Abbreviations Can Application List of Figures Ttcan ConfigurationTtcan Schedule Initialisation Ttcan Message HandlingHelvetica bold Change Control Current StatusChange History ConventionsTerm Meaning Functional Overview Ttcan CpuifcCan Message Transfer Operating Modes Software InitialisationTest Mode Disabled Automatic RetransmissionTest Register addresses 0x0B & 0x0A Ttcan =1 Loop Back combined with Silent Mode Loop Back ModeSoftware control of Pin Cantx No Message RAM ModeAddress Name Reset Value Ttcan Register Summary Hardware Reset DescriptionSIE CCEDAR EIEStatus Register addresses 0x03 No ErrorStatus Interrupts Error Counter addresses 0x05Bit Timing Register addresses 0x07 BRP Extension Register addresses 0x0D & 0x0C Direction = Write IFx Command Mask RegistersArb ClrIntPnd IFx Command Request RegistersDirection = Read ControlIFx Mask Registers BusyMessage Number IFx Message Buffer RegistersIFx Data a and Data B Registers IFx Message Control RegistersMessage Object in the Message Memory Dir ID28-0Msk28-0 Xtd26/77 11.11.02 Interrupt Register addresses 0x09 Message Handler RegistersNew Data Registers Transmission Request RegistersInterrupt Pending Registers Message Valid 1 Register 2 IF1 Data B1 and B2 Registers for Trigger Memory AccessTrigger Number MPr2-0 TT Operation Mode Register addresses 0x29Type TimeMark At CycleCount modRdlc EecsTEW AppWdL TT Interrupt Enable Register addresses 0x31CCM BarkSWE CELGTE GTWRTO TT Cycle Count Register addresses 0x3D & 0x3C TT Error Level Register addresses 0x3F & 0x3ETUR Numerator Conﬁguration Low Register addresses 0x57 TUR Numerator Actual Registers addresses 0x5B & 0x5A TUR Denominator Conﬁguration Register addresses 0x59TT StopWatch Register addresses 0x61 Egtf QCSQgtp EcalSWS TMCDET ECSTMG EPE40/77 11.11.02 Data Transfer Between IFx Registers and Message RAM Internal can Message HandlingStart Transmission of Messages in Event Driven can CommunicationStoring Received Messages in Fifo Buffers Acceptance Filtering of Received MessagesReception of Data Frame Reception of Remote FrameConﬁguration of the Module Receive / Transmit PriorityCanclk input Nominal can Bit Time Sync PropSeg PhaseSeg1 PhaseSeg21 Conﬁguration of the Bit Timing Bit Time and Bit RateBRP Propagation Time SegmentPhase Buffer Segments and Synchronisation Synchronisation on late and early Edges Filtering of Short Dominant Spikes 1.5 Conﬁguration of the can Protocol Controller Oscillator Tolerance RangeCalculation of the Bit Timing Parameters Example for Bit Timing at high Baudrate 2 Conﬁguration of the Message Memory Example for Bit Timing at low Baudrate2.2 Conﬁguration of a Single Receive Object for Data Frames 2.1 Conﬁguration of a Transmit Object for Data Frames2.3 Conﬁguration of a Fifo Buffer Handling of Interrupts Can CommunicationUpdating a Transmit Object Reading from a Fifo Buffer Changing a Transmit ObjectReading Received Messages Requesting New Data for a Receive ObjectCPU Handling of a Fifo Buffer Interrupt Driven Ttcan Timing Ttcan Conﬁguration510 125000 32.5 100/12 529/17 TURMessage Scheduling Trigger Memory 63/77 11.11.02 Reference Message Message ObjectsPeriodic Transmit Message Time Slaves Event Driven Transmit MessagePotential Time Masters Event Driven Messages Ttcan Message Handling Message ReceptionMessage Transmission Periodic MessagesStopwatch Ttcan Gap ControlCycle Time and Global Time Synchronisation Previous RefMark Ttcan Interrupt and Error HandlingConﬁguration Example Rdlc & TEW & CCM Register RemarkType & Msg & CycleCode RTO , TM , L2 , TTMode3 74/77 11.11.02 Interface GenericCustomer Interface Interrupt Timing Timing of the Wait output signalCanclk Canwaitb Busy = ‘1’ Busy = ‘0’EOF