Bosch Appliances TTCAN Direction = Read, Control, ClrIntPnd, IFx Command Request Registers

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TTCAN

User’s Manual

Revision 1.6

manual_about.fm

ClrIntPnd Clear Interrupt Pending Bit

Note : When writing to a Message Object, this bit is ignored.

TxRqst/NewDatAccess Transmission Request Bit one set TxRqst bit

zero TxRqst bit unchanged

Note : If a transmission is requested by setting TxRqst/NewDat in the IFx Command Mask Register, bit TxRqst in the IFx Message Control Register will be ignored.

Data A Access Data Bytes 0-3

one transfer Data Bytes 0-3 to Message Object. zero Data Bytes 0-3 unchanged.

Data B Access Data Bytes 4-7

one transfer Data Bytes 4-7 to Message Object. zero Data Bytes 4-7 unchanged.

3.3.1.2 Direction = Read

Mask Access Mask Bits

one transfer Identiﬁer Mask + MDir + MXtd to IFx Message Buffer Register. zero Mask bits unchanged.

Arb	Access Arbitration Bits
	one	transfer Identiﬁer + Dir + Xtd + MsgVal to IFx Message Buffer Register.
	zero	Arbitration bits unchanged.
Control	Access Control Bits
	one	transfer Control Bits to IFx Message Buffer Register.
	zero	Control Bits unchanged.
ClrIntPnd	Clear Interrupt Pending Bit
	one	clear IntPnd bit in the Message Object.
	zero	IntPnd bit remains unchanged.

TxRqst/NewDatAccess New Data Bit

one clear NewDat bit in the Message Object. zero NewDat bit remains unchanged.

Note : A read access to a Message Object can be combined with the reset of the control bits IntPnd and NewDat. The values of these bits transferred to the IFx Message Control Register always reﬂect the status before resetting them.

Data A Access Data Bytes 0-3

one transfer Data Bytes 0-3 to IFx Message Buffer Register. zero Data Bytes 0-3 unchanged.

Data B Access Data Bytes 4-7

one transfer Data Bytes 4-7 to IFx Message Buffer Register. zero Data Bytes 4-7 unchanged.

Note : The speed of the message transfer does not depend on how many bytes are transferred.

3.3.2 IFx Command Request Registers

A message transfer is started as soon as the CPU has written the message number to low byte of the Command Request Register. With this write operation, the Busy bit is automatically set to ‘1’ to notify the CPU that a transfer is in progress. After a wait time of 3 to

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Contents User’s Manual Robert Bosch GmbHCopyright Notice and Proprietary Information Change Control Functional Overview 2.2. Block Diagram Operating ModesConventions Scope References Terms and Abbreviations Can Application Ttcan Message Handling Ttcan ConfigurationTtcan Schedule Initialisation List of FiguresConventions Change Control Current StatusChange History Helvetica boldTerm Meaning Functional Overview Cpuifc TtcanOperating Modes Software Initialisation Can Message TransferTest Mode Disabled Automatic RetransmissionTest Register addresses 0x0B & 0x0A Ttcan =1 Loop Back Mode Loop Back combined with Silent ModeNo Message RAM Mode Software control of Pin CantxAddress Name Reset Value Hardware Reset Description Ttcan Register SummaryEIE CCEDAR SIENo Error Status Register addresses 0x03Status Interrupts Error Counter addresses 0x05Bit Timing Register addresses 0x07 BRP Extension Register addresses 0x0D & 0x0C Direction = Write IFx Command Mask RegistersArb Control IFx Command Request RegistersDirection = Read ClrIntPndIFx Message Buffer Registers BusyMessage Number IFx Mask RegistersIFx Data a and Data B Registers IFx Message Control RegistersMessage Object in the Message Memory Xtd ID28-0Msk28-0 Dir26/77 11.11.02 Message Handler Registers Interrupt Register addresses 0x09New Data Registers Transmission Request RegistersInterrupt Pending Registers Message Valid 1 Register 2 IF1 Data B1 and B2 Registers for Trigger Memory AccessTrigger Number TimeMark At CycleCount mod TT Operation Mode Register addresses 0x29Type MPr2-0Rdlc EecsTEW Bark TT Interrupt Enable Register addresses 0x31CCM AppWdLGTW CELGTE SWERTO TT Cycle Count Register addresses 0x3D & 0x3C TT Error Level Register addresses 0x3F & 0x3ETUR Numerator Conﬁguration Low Register addresses 0x57 TUR Numerator Actual Registers addresses 0x5B & 0x5A TUR Denominator Conﬁguration Register addresses 0x59TT StopWatch Register addresses 0x61 Ecal QCSQgtp EgtfECS TMCDET SWSEPE TMG40/77 11.11.02 Internal can Message Handling Data Transfer Between IFx Registers and Message RAMTransmission of Messages in Event Driven can Communication StartReception of Remote Frame Acceptance Filtering of Received MessagesReception of Data Frame Storing Received Messages in Fifo BuffersReceive / Transmit Priority Conﬁguration of the ModuleBit Time and Bit Rate Sync PropSeg PhaseSeg1 PhaseSeg21 Conﬁguration of the Bit Timing Canclk input Nominal can Bit TimePropagation Time Segment BRPPhase Buffer Segments and Synchronisation Synchronisation on late and early Edges Filtering of Short Dominant Spikes Oscillator Tolerance Range 1.5 Conﬁguration of the can Protocol ControllerCalculation of the Bit Timing Parameters Example for Bit Timing at high Baudrate Example for Bit Timing at low Baudrate 2 Conﬁguration of the Message Memory2.1 Conﬁguration of a Transmit Object for Data Frames 2.2 Conﬁguration of a Single Receive Object for Data Frames2.3 Conﬁguration of a Fifo Buffer Can Communication Handling of InterruptsUpdating a Transmit Object Requesting New Data for a Receive Object Changing a Transmit ObjectReading Received Messages Reading from a Fifo BufferCPU Handling of a Fifo Buffer Interrupt Driven Ttcan Conﬁguration Ttcan Timing510 125000 32.5 100/12 529/17 TURMessage Scheduling Trigger Memory 63/77 11.11.02 Reference Message Message ObjectsPeriodic Transmit Message Time Slaves Event Driven Transmit MessagePotential Time Masters Periodic Messages Ttcan Message Handling Message ReceptionMessage Transmission Event Driven MessagesTtcan Gap Control StopwatchCycle Time and Global Time Synchronisation Ttcan Interrupt and Error Handling Previous RefMarkConﬁguration Example Register Remark Rdlc & TEW & CCMType & Msg & CycleCode RTO , TM , L2 , TTMode3 74/77 11.11.02 Interface GenericCustomer Interface Busy = ‘1’ Busy = ‘0’ Timing of the Wait output signalCanclk Canwaitb Interrupt TimingEOF