Bosch Appliances TTCAN user manual 63/77 11.11.02

Page 63

TTCAN

User’s Manual

Revision 1.6

manual_about.fm

for Arbitrating Time Windows, Tx_Trigger_Merged may be used only for Merged Arbitrating Time Windows. The last Tx_Trigger of a Merged Arbitrating Time Window must be of the type Tx_Trigger_Single. A Configuration Error (Error level 3) is detected when a Trigger of the type Tx_Trigger_Merged is followed by any other Trigger than one of the type Tx_Trigger_Single or Tx_Trigger_Merged. Several Tx_Triggers may be defined for the same Message Object. Depending on their Cycle_Code, they may be ignored in some Basic Cycles. The Cycle_Code has to be considered when ETT is calculated.

Rx_Trigger is used to check for the reception of periodic messages in Exclusive Time Windows. The Time Mark of an Rx_Trigger shall be placed after the end of that message’s transmission, independent of Time Window boundaries. Several Rx_Triggers may be defined for the same Message Object. Depending on their Cycle_Code, they may be ignored in some Basic Cycles.

EndOfList is an illegal Trigger type, a Configuration Error (Error level 3) is detected when an EndOfList Trigger is encountered in the Trigger Memory.

The Trigger information is written into the Trigger Memory using the IF1 Data B1 and IF1 Data B2 registers and the Trigger Memory Access Register, similar to the configuration of Message Objects. On each transfer, 32 bits are loaded either from the IF1 Data B1 and B2 Registers to the selected Trigger Memory word or vice versa. Write access to the Trigger Memory is locked when the Configuration Mode is left.

The Triggers in the Trigger Memory have to be sorted by their Time_Marks, the Trigger with the lowest Time_Mark is written to the first Trigger Memory word.

Note : If the Reference Message is n NTU long, then a Trigger with a Time_Mark<n will never become active and will be treated as a Configuration Error.

Starting point of the Cycle Time is the Sample Point of the Reference Message’s Start of Frame bit. The next Reference Message is requested when Cycle Time reaches the Tx_Ref_Trigger’s Time_Mark. The CAN_Core reacts on the transmission request at the next Sample Point. A new Sync_Mark is captured at the Start of Frame bit, but the Cycle Time is incremented until the Reference Message is successfully transmitted (or received) and the Sync_Mark is taken as the new Ref_Mark. At that point of time, Cycle Time is restarted. As a consequence, Cycle Time can never (with the exception of initialisation) be seen at a value<n, with n being the length of the Reference Message measured in NTU. The length of the Basic Cycle is Tx_Ref_Trigger’s Time_Mark+(1NTU+1CAN bit time).

The Trigger List will be different for all nodes in the TTCAN network, each node knows only the Tx_Triggers for its own transmit messages, the Rx_Triggers for those receive messages that are processed by this node, and the Triggers concerning the Reference Messages.

The following restrictions exist for the node’s Trigger List :

There may not be two Triggers that are active at the same Cycle Time and Cycle_Count, but Triggers that are active in different Basic Cycles may share the same Time_Mark.

Rx_Triggers may not be placed inside Merged Arbitration Windows or inside the Tx_Enable Windows of other Tx_Triggers, but they may be placed after the Tx_Ref_Trigger.

Triggers that are placed after the Watch_Trigger (or after the Watch_Trigger_Gap when SyncSt is In_Gap) will never become active, the Watch_Triggers themselves will not become active when the Reference Messages are transmitted on time.

All unused Trigger Memory words (after the Watch_Trigger or after the Watch_Trigger_Gap when SyncSt is In_Gap) must be set to Trigger Type EndOfList.

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Contents Robert Bosch GmbH User’s ManualCopyright Notice and Proprietary Information Functional Overview 2.2. Block Diagram Operating Modes Change ControlConventions Scope References Terms and Abbreviations Can Application List of Figures Ttcan ConfigurationTtcan Schedule Initialisation Ttcan Message HandlingHelvetica bold Change Control Current StatusChange History ConventionsTerm Meaning Functional Overview Ttcan CpuifcCan Message Transfer Operating Modes Software InitialisationDisabled Automatic Retransmission Test ModeTest Register addresses 0x0B & 0x0A Ttcan =1 Loop Back combined with Silent Mode Loop Back ModeSoftware control of Pin Cantx No Message RAM ModeAddress Name Reset Value Ttcan Register Summary Hardware Reset DescriptionSIE CCEDAR EIEStatus Register addresses 0x03 No ErrorError Counter addresses 0x05 Status InterruptsBit Timing Register addresses 0x07 BRP Extension Register addresses 0x0D & 0x0C IFx Command Mask Registers Direction = WriteArb ClrIntPnd IFx Command Request RegistersDirection = Read ControlIFx Mask Registers BusyMessage Number IFx Message Buffer RegistersIFx Message Control Registers IFx Data a and Data B RegistersMessage Object in the Message Memory Dir ID28-0Msk28-0 Xtd26/77 11.11.02 Interrupt Register addresses 0x09 Message Handler RegistersTransmission Request Registers New Data RegistersInterrupt Pending Registers 2 IF1 Data B1 and B2 Registers for Trigger Memory Access Message Valid 1 RegisterTrigger Number MPr2-0 TT Operation Mode Register addresses 0x29Type TimeMark At CycleCount modEecs RdlcTEW AppWdL TT Interrupt Enable Register addresses 0x31CCM BarkSWE CELGTE GTWRTO TT Error Level Register addresses 0x3F & 0x3E TT Cycle Count Register addresses 0x3D & 0x3CTUR Numerator Configuration Low Register addresses 0x57 TUR Denominator Configuration Register addresses 0x59 TUR Numerator Actual Registers addresses 0x5B & 0x5ATT StopWatch Register addresses 0x61 Egtf QCSQgtp EcalSWS TMCDET ECSTMG EPE40/77 11.11.02 Data Transfer Between IFx Registers and Message RAM Internal can Message HandlingStart Transmission of Messages in Event Driven can CommunicationStoring Received Messages in Fifo Buffers Acceptance Filtering of Received MessagesReception of Data Frame Reception of Remote FrameConfiguration of the Module Receive / Transmit PriorityCanclk input Nominal can Bit Time Sync PropSeg PhaseSeg1 PhaseSeg21 Configuration of the Bit Timing Bit Time and Bit RateBRP Propagation Time SegmentPhase Buffer Segments and Synchronisation Synchronisation on late and early Edges Filtering of Short Dominant Spikes 1.5 Configuration of the can Protocol Controller Oscillator Tolerance RangeCalculation of the Bit Timing Parameters Example for Bit Timing at high Baudrate 2 Configuration of the Message Memory Example for Bit Timing at low Baudrate2.2 Configuration of a Single Receive Object for Data Frames 2.1 Configuration of a Transmit Object for Data Frames2.3 Configuration of a Fifo Buffer Handling of Interrupts Can CommunicationUpdating a Transmit Object Reading from a Fifo Buffer Changing a Transmit ObjectReading Received Messages Requesting New Data for a Receive ObjectCPU Handling of a Fifo Buffer Interrupt Driven Ttcan Timing Ttcan ConfigurationTUR 510 125000 32.5 100/12 529/17Message Scheduling Trigger Memory 63/77 11.11.02 Message Objects Reference MessagePeriodic Transmit Message Event Driven Transmit Message Time SlavesPotential Time Masters Event Driven Messages Ttcan Message Handling Message ReceptionMessage Transmission Periodic MessagesStopwatch Ttcan Gap ControlCycle Time and Global Time Synchronisation Previous RefMark Ttcan Interrupt and Error HandlingConfiguration Example Rdlc & TEW & CCM Register RemarkType & Msg & CycleCode RTO , TM , L2 , TTMode3 74/77 11.11.02 Generic InterfaceCustomer Interface Interrupt Timing Timing of the Wait output signalCanclk Canwaitb Busy = ‘1’ Busy = ‘0’EOF
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