Bosch Appliances TTCAN Change Control Current Status, Change History, Conventions, Helvetica bold

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TTCAN

User’s Manual

Revision 1.6

1. About this Document

manual_about.fm

1.1Change Control

1.1.1Current Status

Revision 1.6

1.1.2 Change History
Issue	Date	By	Change
Draft 0.0	30.06.00	F. Hartwich	First Draft
Revision 0.1	12.01.01	F. Hartwich	Gap Control
Revision 0.2	21.10.00	F. Hartwich	Trigger Memory
Revision 1.0	29.11.00	F. Hartwich	Cycle Count, Global Time Mark
Revision 1.1	11.12.00	F. Hartwich	TUR Conﬁguration, Enable Local Time
Revision 1.2	13.12.00	F. Hartwich	Time Mark Register, TMC
Revision 1.3	17.01.01	F. Hartwich	TUR Conﬁguration Registers
Revision 1.4	30.04.01	F. Hartwich	Clock Synch., Stop_Watch, External Events
Revision 1.5	12.10.01	F. Hartwich	Editorial changes
Revision 1.6	11.11.02	F. Hartwich	Watchdog, Gap Control, Global Time Preset

1.2 Conventions

The following conventions are used within this User’s Manual.

Helvetica bold	Names of bits and signals
Helvetica italic	States of bits and signals

1.3 Scope

This document describes the TTCAN IP module and its features from the application programmer’s point of view.

All information necessary to integrate the TTCAN IP module into an user-deﬁned ASIC is located in the ‘Module Integration Guide’.

1.4 References

This document refers to the following documents.

Ref	Author(s)	Title
1	FV/SLN1	CAN Speciﬁcation Revision 2.0
2	K8/EIS1	Module Integration Guide
3	K8/EIS1	VHDL Reference CAN User’s Manual
4	ISO	ISO 11898-1 “Controller Area Network (CAN) - Part 1:
		Data link layer and physical signalling”
5	ISO	ISO 11898-4 “Controller Area Network (CAN) - Part 4:
		Time triggered communication”

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Contents User’s Manual Robert Bosch GmbHCopyright Notice and Proprietary Information Functional Overview 2.2. Block Diagram Operating Modes Change ControlConventions Scope References Terms and Abbreviations Can Application Ttcan Message Handling Ttcan ConfigurationTtcan Schedule Initialisation List of FiguresConventions Change Control Current StatusChange History Helvetica boldTerm Meaning Functional Overview Cpuifc TtcanOperating Modes Software Initialisation Can Message TransferDisabled Automatic Retransmission Test ModeTest Register addresses 0x0B & 0x0A Ttcan =1 Loop Back Mode Loop Back combined with Silent ModeNo Message RAM Mode Software control of Pin CantxAddress Name Reset Value Hardware Reset Description Ttcan Register SummaryEIE CCEDAR SIENo Error Status Register addresses 0x03Error Counter addresses 0x05 Status InterruptsBit Timing Register addresses 0x07 BRP Extension Register addresses 0x0D & 0x0C IFx Command Mask Registers Direction = WriteArb Control IFx Command Request RegistersDirection = Read ClrIntPndIFx Message Buffer Registers BusyMessage Number IFx Mask RegistersIFx Message Control Registers IFx Data a and Data B RegistersMessage Object in the Message Memory Xtd ID28-0Msk28-0 Dir26/77 11.11.02 Message Handler Registers Interrupt Register addresses 0x09Transmission Request Registers New Data RegistersInterrupt Pending Registers 2 IF1 Data B1 and B2 Registers for Trigger Memory Access Message Valid 1 RegisterTrigger Number TimeMark At CycleCount mod TT Operation Mode Register addresses 0x29Type MPr2-0Eecs RdlcTEW Bark TT Interrupt Enable Register addresses 0x31CCM AppWdLGTW CELGTE SWERTO TT Error Level Register addresses 0x3F & 0x3E TT Cycle Count Register addresses 0x3D & 0x3CTUR Numerator Conﬁguration Low Register addresses 0x57 TUR Denominator Conﬁguration Register addresses 0x59 TUR Numerator Actual Registers addresses 0x5B & 0x5ATT StopWatch Register addresses 0x61 Ecal QCSQgtp EgtfECS TMCDET SWSEPE TMG40/77 11.11.02 Internal can Message Handling Data Transfer Between IFx Registers and Message RAMTransmission of Messages in Event Driven can Communication StartReception of Remote Frame Acceptance Filtering of Received MessagesReception of Data Frame Storing Received Messages in Fifo BuffersReceive / Transmit Priority Conﬁguration of the ModuleBit Time and Bit Rate Sync PropSeg PhaseSeg1 PhaseSeg21 Conﬁguration of the Bit Timing Canclk input Nominal can Bit TimePropagation Time Segment BRPPhase Buffer Segments and Synchronisation Synchronisation on late and early Edges Filtering of Short Dominant Spikes Oscillator Tolerance Range 1.5 Conﬁguration of the can Protocol ControllerCalculation of the Bit Timing Parameters Example for Bit Timing at high Baudrate Example for Bit Timing at low Baudrate 2 Conﬁguration of the Message Memory2.1 Conﬁguration of a Transmit Object for Data Frames 2.2 Conﬁguration of a Single Receive Object for Data Frames2.3 Conﬁguration of a Fifo Buffer Can Communication Handling of InterruptsUpdating a Transmit Object Requesting New Data for a Receive Object Changing a Transmit ObjectReading Received Messages Reading from a Fifo BufferCPU Handling of a Fifo Buffer Interrupt Driven Ttcan Conﬁguration Ttcan TimingTUR 510 125000 32.5 100/12 529/17Message Scheduling Trigger Memory 63/77 11.11.02 Message Objects Reference MessagePeriodic Transmit Message Event Driven Transmit Message Time SlavesPotential Time Masters Periodic Messages Ttcan Message Handling Message ReceptionMessage Transmission Event Driven MessagesTtcan Gap Control StopwatchCycle Time and Global Time Synchronisation Ttcan Interrupt and Error Handling Previous RefMarkConﬁguration Example Register Remark Rdlc & TEW & CCMType & Msg & CycleCode RTO , TM , L2 , TTMode3 74/77 11.11.02 Generic InterfaceCustomer Interface Busy = ‘1’ Busy = ‘0’ Timing of the Wait output signalCanclk Canwaitb Interrupt TimingEOF