Bosch Appliances TTCAN user manual Ttcan Message Handling Message Reception, Message Transmission

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TTCAN

User’s Manual

Revision 1.6

manual_about.fm

reset or configuration, giving no acknowledge). When it reaches Initial_Watch_Trigger (not part of the Trigger List, defined as maximum of Cycle Time), the attempted transmission is aborted, IWT in the Interrupt Vector register is set, the FSE is frozen, and the Cycle Time will become invalid, but the node will still be able to take part in CAN bus communication (to give acknowledge or to send error flags). Resetting IWT will restart the FSE and Cycle Time, the FSE will not be restarted by the reception of a Reference Message.

When a Potential Time Master reaches the Watch_Triggers after it has received any message but the Reference Message, it will assume a Fatal Error (Error Level 3), set WTr in the Interrupt Vector register, switch off its CAN bus output, and enter the Bus Monitoring Mode. In the Bus Monitoring Mode, it is still able to receive messages, but it cannot send any dominant bits (e.g. cannot give acknowledge). The Fatal Error state can be left via a re-configuration.

When no error is encountered during initialisation, the first Reference Message will put SyncST to Synchronising and the second will put it (depending on its Next_is_Gap bit) into In_Schedule or In_Gap, enabling all Tx_Triggers and Rx_Triggers.

A Potential Time Master will be in MState Current Time Master when it was the transmitter of the last Reference Message, else it will be in MState Backup Time Master.

When all Potential Time Masters have finished Configuration, the node with the highest Time Master Priority in the network will become the Current Time Master.

5.3TTCAN Message Handling

5.3.1Message Reception

In TTCAN, the handling of received message is the same as in Event driven CAN Communication, see chapter 4.1.3.1. The message’s MSC will be updated at the message’s Rx_Trigger(s) and gives additional means to check whether the received data arrived on time.

5.3.2 Message Transmission

In TTCAN, the handling of message to be transmitted is similar as in “Event driven CAN Communication”, see chapter 4.1.2. The differences for periodic messages and event driven messages are described in the following sections.

5.3.2.1 Periodic Messages

Neither TxRqst nor Newdat are changed from their preconfigured values. The application program has to update the data regularly and on time, synchronised to the Cycle Time. TTCAN’s CPU interface structure guarantees that no partially updated messages are transmitted. The message’s MSC provides information on the success of the transmission. The transmission may be temporarily disabled by resetting MsgLst or NewDat.

5.3.2.2 Event Driven Messages

The message data may be updated asynchronously to the Cycle Time, the transmission of the event driven message inside an Arbitrating Time Window is requested by setting both TxRqst and NewDat to ‘1’. The actual transmission is started time triggered when Cycle Time reaches the Time_Mark of the Tx_Trigger_Single or Tx_Trigger_Merged configured for the Message Object. Different from “Event driven CAN Communication”, the success of the transmission is indicated when the Message Handler resets NewDat while TxRqst remains unchanged. The MSC of an event driven message is not updated. When the transmission was not successful (lost arbitration or disturbance), it will be repeated next time (one of) its Tx_Trigger(s) become(s) active. When the transmission attempt was inside a Merged Arbitrating Time

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Contents User’s Manual Robert Bosch GmbHCopyright Notice and Proprietary Information Functional Overview 2.2. Block Diagram Operating Modes Change ControlConventions Scope References Terms and Abbreviations Can Application Ttcan Message Handling Ttcan ConfigurationTtcan Schedule Initialisation List of FiguresConventions Change Control Current StatusChange History Helvetica boldTerm Meaning Functional Overview Cpuifc TtcanOperating Modes Software Initialisation Can Message TransferDisabled Automatic Retransmission Test ModeTest Register addresses 0x0B & 0x0A Ttcan =1 Loop Back Mode Loop Back combined with Silent ModeNo Message RAM Mode Software control of Pin CantxAddress Name Reset Value Hardware Reset Description Ttcan Register SummaryEIE CCEDAR SIENo Error Status Register addresses 0x03Error Counter addresses 0x05 Status InterruptsBit Timing Register addresses 0x07 BRP Extension Register addresses 0x0D & 0x0C IFx Command Mask Registers Direction = WriteArb Control IFx Command Request RegistersDirection = Read ClrIntPndIFx Message Buffer Registers BusyMessage Number IFx Mask RegistersIFx Message Control Registers IFx Data a and Data B RegistersMessage Object in the Message Memory Xtd ID28-0Msk28-0 Dir26/77 11.11.02 Message Handler Registers Interrupt Register addresses 0x09Transmission Request Registers New Data RegistersInterrupt Pending Registers 2 IF1 Data B1 and B2 Registers for Trigger Memory Access Message Valid 1 RegisterTrigger Number TimeMark At CycleCount mod TT Operation Mode Register addresses 0x29Type MPr2-0Eecs RdlcTEW Bark TT Interrupt Enable Register addresses 0x31CCM AppWdLGTW CELGTE SWERTO TT Error Level Register addresses 0x3F & 0x3E TT Cycle Count Register addresses 0x3D & 0x3CTUR Numerator Configuration Low Register addresses 0x57 TUR Denominator Configuration Register addresses 0x59 TUR Numerator Actual Registers addresses 0x5B & 0x5ATT StopWatch Register addresses 0x61 Ecal QCSQgtp EgtfECS TMCDET SWSEPE TMG40/77 11.11.02 Internal can Message Handling Data Transfer Between IFx Registers and Message RAMTransmission of Messages in Event Driven can Communication StartReception of Remote Frame Acceptance Filtering of Received MessagesReception of Data Frame Storing Received Messages in Fifo BuffersReceive / Transmit Priority Configuration of the ModuleBit Time and Bit Rate Sync PropSeg PhaseSeg1 PhaseSeg21 Configuration of the Bit Timing Canclk input Nominal can Bit TimePropagation Time Segment BRPPhase Buffer Segments and Synchronisation Synchronisation on late and early Edges Filtering of Short Dominant Spikes Oscillator Tolerance Range 1.5 Configuration of the can Protocol ControllerCalculation of the Bit Timing Parameters Example for Bit Timing at high Baudrate Example for Bit Timing at low Baudrate 2 Configuration of the Message Memory2.1 Configuration of a Transmit Object for Data Frames 2.2 Configuration of a Single Receive Object for Data Frames2.3 Configuration of a Fifo Buffer Can Communication Handling of InterruptsUpdating a Transmit Object Requesting New Data for a Receive Object Changing a Transmit ObjectReading Received Messages Reading from a Fifo BufferCPU Handling of a Fifo Buffer Interrupt Driven Ttcan Configuration Ttcan TimingTUR 510 125000 32.5 100/12 529/17Message Scheduling Trigger Memory 63/77 11.11.02 Message Objects Reference MessagePeriodic Transmit Message Event Driven Transmit Message Time SlavesPotential Time Masters Periodic Messages Ttcan Message Handling Message ReceptionMessage Transmission Event Driven MessagesTtcan Gap Control StopwatchCycle Time and Global Time Synchronisation Ttcan Interrupt and Error Handling Previous RefMarkConfiguration Example Register Remark Rdlc & TEW & CCMType & Msg & CycleCode RTO , TM , L2 , TTMode3 74/77 11.11.02 Generic InterfaceCustomer Interface Busy = ‘1’ Busy = ‘0’ Timing of the Wait output signalCanclk Canwaitb Interrupt TimingEOF
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