Bosch Appliances TTCAN user manual 2.1 Configuration of a Transmit Object for Data Frames

Page 54

TTCAN

User’s Manual

Revision 1.6

manual_about.fm

The CPU may poll all MessageObject’s NewDat and TxRqst bits in parallel, in the New Data x Registers and in the Transmission Request x Registers. Polling is made easier if all Transmit Objects are grouped at the low numbers, all Receive Objects are grouped at the high numbers.

The internal prioritisation of the Transmit Objects is controlled by their Message Number, so the most urgent message should be configured for the first Message Object.

The acceptance filtering for received Data Frames or Remote Frames is done in ascending order of Message Objects, so a frame that has been accepted by one Message Object cannot be accepted by another Message Object with a higher Message Number. The last Message Object may be configured to accept any Data Frame or Remote Frame that was not accepted by any other Message Object, for nodes that need to log the complete message traffic on the CAN bus.

It is not necessary to configure Transmit Objects for the transmission of Remote Frames. Setting TxRqst for a Receive Object will cause the transmission of a Remote Frame with the same identifier as the Data Frame for that this receive Object is configured.

Received Remote Frames do not require a Receive Object, they will, if in the matching Transmit Object the RmtEn bit is set, trigger automatically the transmission of a Data Frame.

4.2.2.1 Configuration of a Transmit Object for Data Frames

Figure 14 shows how a Transmit Object should be initialised.

MsgVal

Arb

Data

Mask

EoB

Dir

NewDat

MsgLst

RxIE

TxIE

IntPnd

RmtEn

TxRqst

 

 

 

 

 

 

 

 

 

 

 

 

 

1

appl.

appl.

appl.

1

1

0

0

0

appl.

0

appl.

0

 

 

 

 

 

 

 

 

 

 

 

 

 

Figure 14: Initialisation of a Transmit Object

The Arbitration Registers (ID28-0and Xtd bit) are given by the application. They define the identifier and type of the outgoing message. If an 11-bit Identifier (“Standard Frame”) is used (Xtd = ‘0’), it is programmed to ID28 - ID18, ID17 - ID0 can then be disregarded.

The Data Registers (DLC3-0, Data0-7) are given by the application, TxRqst and RmtEn may not be set before the data is valid.

If the TxIE bit is set, the IntPnd bit will be set after a successful transmission of the Message Object.

If the RmtEn bit is set, a matching received Remote Frame will cause the TxRqst bit to be set; the Remote Frame will autonomously be answered by a Data Frame.

The Mask Registers (Msk28-0, UMask, MXtd, and MDir bits) may be used (UMask=’1’) to allow groups of Remote Frames with similar identifiers to set the TxRqst bit. The Dir bit should not be masked. For details see section 4.1.3.2, handle with care. Identifier masking must be disabled (UMask = ‘0’) if no Remote Frames are allowed to set the TxRqst bit (RmtEn = ‘0’).

4.2.2.2 Configuration of a Single Receive Object for Data Frames

Figure 14 shows how a Receive Object should be initialised.

MsgVal

Arb

Data

Mask

EoB

Dir

NewDat

MsgLst

RxIE

TxIE

IntPnd

RmtEn

TxRqst

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

appl.

appl.

appl.

1

0

0

 

0

appl.

0

0

0

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Figure 15: Initialisation of a single Receive

Object

 

 

 

 

 

BOSCH

- 54/77 -

11.11.02

Page 53 Page 55
Image 54
Page 53 Page 55
Contents User’s Manual Robert Bosch GmbHCopyright Notice and Proprietary Information Functional Overview 2.2. Block Diagram Operating Modes Change ControlConventions Scope References Terms and Abbreviations Can Application Ttcan Message Handling Ttcan ConfigurationTtcan Schedule Initialisation List of FiguresConventions Change Control Current StatusChange History Helvetica boldTerm Meaning Functional Overview Cpuifc TtcanOperating Modes Software Initialisation Can Message TransferDisabled Automatic Retransmission Test ModeTest Register addresses 0x0B & 0x0A Ttcan =1 Loop Back Mode Loop Back combined with Silent ModeNo Message RAM Mode Software control of Pin CantxAddress Name Reset Value Hardware Reset Description Ttcan Register SummaryEIE CCEDAR SIENo Error Status Register addresses 0x03Error Counter addresses 0x05 Status InterruptsBit Timing Register addresses 0x07 BRP Extension Register addresses 0x0D & 0x0C IFx Command Mask Registers Direction = WriteArb Control IFx Command Request RegistersDirection = Read ClrIntPndIFx Message Buffer Registers BusyMessage Number IFx Mask RegistersIFx Message Control Registers IFx Data a and Data B RegistersMessage Object in the Message Memory Xtd ID28-0Msk28-0 Dir26/77 11.11.02 Message Handler Registers Interrupt Register addresses 0x09Transmission Request Registers New Data RegistersInterrupt Pending Registers 2 IF1 Data B1 and B2 Registers for Trigger Memory Access Message Valid 1 RegisterTrigger Number TimeMark At CycleCount mod TT Operation Mode Register addresses 0x29Type MPr2-0Eecs RdlcTEW Bark TT Interrupt Enable Register addresses 0x31CCM AppWdLGTW CELGTE SWERTO TT Error Level Register addresses 0x3F & 0x3E TT Cycle Count Register addresses 0x3D & 0x3CTUR Numerator Configuration Low Register addresses 0x57 TUR Denominator Configuration Register addresses 0x59 TUR Numerator Actual Registers addresses 0x5B & 0x5ATT StopWatch Register addresses 0x61 Ecal QCSQgtp EgtfECS TMCDET SWSEPE TMG40/77 11.11.02 Internal can Message Handling Data Transfer Between IFx Registers and Message RAMTransmission of Messages in Event Driven can Communication StartReception of Remote Frame Acceptance Filtering of Received MessagesReception of Data Frame Storing Received Messages in Fifo BuffersReceive / Transmit Priority Configuration of the ModuleBit Time and Bit Rate Sync PropSeg PhaseSeg1 PhaseSeg21 Configuration of the Bit Timing Canclk input Nominal can Bit TimePropagation Time Segment BRPPhase Buffer Segments and Synchronisation Synchronisation on late and early Edges Filtering of Short Dominant Spikes Oscillator Tolerance Range 1.5 Configuration of the can Protocol ControllerCalculation of the Bit Timing Parameters Example for Bit Timing at high Baudrate Example for Bit Timing at low Baudrate 2 Configuration of the Message Memory2.1 Configuration of a Transmit Object for Data Frames 2.2 Configuration of a Single Receive Object for Data Frames2.3 Configuration of a Fifo Buffer Can Communication Handling of InterruptsUpdating a Transmit Object Requesting New Data for a Receive Object Changing a Transmit ObjectReading Received Messages Reading from a Fifo BufferCPU Handling of a Fifo Buffer Interrupt Driven Ttcan Configuration Ttcan TimingTUR 510 125000 32.5 100/12 529/17Message Scheduling Trigger Memory 63/77 11.11.02 Message Objects Reference MessagePeriodic Transmit Message Event Driven Transmit Message Time SlavesPotential Time Masters Periodic Messages Ttcan Message Handling Message ReceptionMessage Transmission Event Driven MessagesTtcan Gap Control StopwatchCycle Time and Global Time Synchronisation Ttcan Interrupt and Error Handling Previous RefMarkConfiguration Example Register Remark Rdlc & TEW & CCMType & Msg & CycleCode RTO , TM , L2 , TTMode3 74/77 11.11.02 Generic InterfaceCustomer Interface Busy = ‘1’ Busy = ‘0’ Timing of the Wait output signalCanclk Canwaitb Interrupt TimingEOF
Top Page Image Contents