Bosch Appliances TTCAN user manual TUR Denominator Configuration Register addresses 0x59

Page 36

TTCAN

User’s Manual

Revision 1.6

manual_about.fm

3.5.16 TUR Denominator Configuration Register (addresses 0x59 & 0x58)

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

 

 

res

 

 

 

 

 

 

DenomCfg[13…0]

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

r

 

 

 

 

 

 

 

rw

 

 

 

 

 

 

DenomCfg[13…0] TUR Denominator Configuration

 

 

 

 

 

 

 

 

 

0x0000

 

Illegal value.

 

 

 

 

 

 

 

 

 

 

 

0x0001-0x3FFF DenomCfg[13… 0].

 

 

 

 

 

 

 

The length of the NTU is given by (NumCfg • System Clock Period) = (DenomCfg • NTU), or NTU = System Clock Period • NumCfg/DenomCfg.

DenomCfg is set to 0x1000 by hardware reset and it may not be written to 0x0000. For TTCAN Level 2 it is required that NumCfg≥8•DenomCfg. For TTCAN Level 1 it is required that NumCfg ≥4•DenomCfg and NTU=CAN bit time. Write access to the TUR Denominator Configuration Register is only possible during Configuration Mode and additionally requires that ELT = ’0’.

Note : If NumCfg<7•DenomCfg in TTCAN Level 1, then it is required that subsequent Time_Marks in the Trigger Memory must differ by at least 2 NTU.

3.5.17 TUR Numerator Actual Registers (addresses 0x5B & 0x5A)

 

TUR Numerator ActualL Register

15 14 13 12 11 10 9

8

7 6 5 4 3 2

1

0

 

(addresses 0x5B & 0x5A)

 

 

 

 

 

NumAct[15…8]

 

NumAct[7…0]

 

 

 

 

 

 

 

 

TUR Numerator ActualH Register

res

 

res

NumAct[17,16]

 

(addresses 0x5D & 0x5C)

 

 

 

 

 

 

r

 

r

 

 

 

 

 

 

 

 

 

 

 

 

 

 

NumAct TUR Numerator Actual Value

 

 

 

 

 

≤0x0EFFF

invalid value.

 

 

 

 

 

0x0F000-0x20FFF NumAct[17…0].

 

 

 

 

 

≥0x21000

invalid value.

 

 

 

 

There is no drift compensation in TTCAN Level 1, NumAct = NumCfg. In TTCAN Level 2, the drift between local clock and the time master’s local clock is calculated. The drift is

compensated when the Synchronisation Deviation (difference between NumCfg and the calculated new NumAct) is not more than 2(ldSDL+5). With ldSDL≤7, this results in a

maximum range for NumAct of (NumCfg - 0x1000) ≤ NumAct ≤ (NumCfg + 0x1000)

3.5.18 TT Stop_Watch Register (addresses 0x61 & 0x60)

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

 

 

 

 

 

 

 

Stop_Watch

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

r

 

 

 

 

 

 

 

r

 

 

 

Stop_Watch Stop Watch Register

0x0000-0xFFFF Stop_Watch[15…0]

On a rising edge of the STOP_WATCH_TRIGGER pin, when SWS in the TT Clock Control Register is > 0 and SWE in the TT Interrupt Vector register is ‘0’, the actual value of the time selected by SWS will be copied into the Stop_Watch register and SWE will be set to ‘1’.

Note : The next Stop_Watch timing will be enabled by resetting SWE to ‘0’.

BOSCH

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11.11.02

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Contents User’s Manual Robert Bosch GmbHCopyright Notice and Proprietary Information Functional Overview 2.2. Block Diagram Operating Modes Change ControlConventions Scope References Terms and Abbreviations Can Application Ttcan Configuration Ttcan Schedule InitialisationTtcan Message Handling List of FiguresChange Control Current Status Change HistoryConventions Helvetica boldTerm Meaning Functional Overview Cpuifc TtcanOperating Modes Software Initialisation Can Message TransferDisabled Automatic Retransmission Test ModeTest Register addresses 0x0B & 0x0A Ttcan =1 Loop Back Mode Loop Back combined with Silent ModeNo Message RAM Mode Software control of Pin CantxAddress Name Reset Value Hardware Reset Description Ttcan Register SummaryCCE DAREIE SIENo Error Status Register addresses 0x03Error Counter addresses 0x05 Status InterruptsBit Timing Register addresses 0x07 BRP Extension Register addresses 0x0D & 0x0C IFx Command Mask Registers Direction = WriteArb IFx Command Request Registers Direction = ReadControl ClrIntPndBusy Message NumberIFx Message Buffer Registers IFx Mask RegistersIFx Message Control Registers IFx Data a and Data B RegistersMessage Object in the Message Memory ID28-0 Msk28-0Xtd Dir26/77 11.11.02 Message Handler Registers Interrupt Register addresses 0x09Transmission Request Registers New Data RegistersInterrupt Pending Registers 2 IF1 Data B1 and B2 Registers for Trigger Memory Access Message Valid 1 RegisterTrigger Number TT Operation Mode Register addresses 0x29 TypeTimeMark At CycleCount mod MPr2-0Eecs RdlcTEW TT Interrupt Enable Register addresses 0x31 CCMBark AppWdLCEL GTEGTW SWERTO TT Error Level Register addresses 0x3F & 0x3E TT Cycle Count Register addresses 0x3D & 0x3CTUR Numerator Configuration Low Register addresses 0x57 TUR Denominator Configuration Register addresses 0x59 TUR Numerator Actual Registers addresses 0x5B & 0x5ATT StopWatch Register addresses 0x61 QCS QgtpEcal EgtfTMC DETECS SWSEPE TMG40/77 11.11.02 Internal can Message Handling Data Transfer Between IFx Registers and Message RAMTransmission of Messages in Event Driven can Communication StartAcceptance Filtering of Received Messages Reception of Data FrameReception of Remote Frame Storing Received Messages in Fifo BuffersReceive / Transmit Priority Configuration of the ModuleSync PropSeg PhaseSeg1 PhaseSeg2 1 Configuration of the Bit TimingBit Time and Bit Rate Canclk input Nominal can Bit TimePropagation Time Segment BRPPhase Buffer Segments and Synchronisation Synchronisation on late and early Edges Filtering of Short Dominant Spikes Oscillator Tolerance Range 1.5 Configuration of the can Protocol ControllerCalculation of the Bit Timing Parameters Example for Bit Timing at high Baudrate Example for Bit Timing at low Baudrate 2 Configuration of the Message Memory2.1 Configuration of a Transmit Object for Data Frames 2.2 Configuration of a Single Receive Object for Data Frames2.3 Configuration of a Fifo Buffer Can Communication Handling of InterruptsUpdating a Transmit Object Changing a Transmit Object Reading Received MessagesRequesting New Data for a Receive Object Reading from a Fifo BufferCPU Handling of a Fifo Buffer Interrupt Driven Ttcan Configuration Ttcan TimingTUR 510 125000 32.5 100/12 529/17Message Scheduling Trigger Memory 63/77 11.11.02 Message Objects Reference MessagePeriodic Transmit Message Event Driven Transmit Message Time SlavesPotential Time Masters Ttcan Message Handling Message Reception Message TransmissionPeriodic Messages Event Driven MessagesTtcan Gap Control StopwatchCycle Time and Global Time Synchronisation Ttcan Interrupt and Error Handling Previous RefMarkConfiguration Example Register Remark Rdlc & TEW & CCMType & Msg & CycleCode RTO , TM , L2 , TTMode3 74/77 11.11.02 Generic InterfaceCustomer Interface Timing of the Wait output signal Canclk CanwaitbBusy = ‘1’ Busy = ‘0’ Interrupt TimingEOF
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