Bosch Appliances TTCAN Busy, Message Number, IFx Message Buffer Registers, IFx Mask Registers

Page 23

TTCAN

User’s Manual

Revision 1.6

manual_about.fm

6 CAN_CLK periods, the transfer between the Interface Register and the Message RAM has completed and the Busy bit is cleared to ‘0’. The upper limit of the wait time occurs when the message transfer coincides with a CAN message transmission, acceptance filtering, or message storage. If the CPU-IFC is implemented with the wait-function, the CPU is halted while the Busy bit is set. If the CPU writes to both Command Request Registers consecutively (requests a second transfer while another transfer is already in progress), the second transfer starts when the first one is completed.

 

IF1 Command Request Register

15

14

13 12 11 10 9 8

7 6

5

4 3 2 1 0

 

 

(addresses 0x11 & 0x10)

 

 

 

 

 

 

 

 

Busy

 

res

res

 

Message Number

 

 

 

 

 

 

 

 

 

IF2 Command Request Register

Busy

 

res

res

 

Message Number

 

 

(addresses 0x41 & 0x40)

 

 

 

 

 

 

 

 

r

 

r

r

 

rw

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Busy

Busy Flag

 

 

 

 

 

 

 

 

one

set to one when writing to the IFx Command Request Register

 

 

zero reset to zero when read/write action has finished.

 

Message Number

0x01-0x20Valid Message Number, the Message Object in the Message RAM is selected for data transfer.

0x00Not a valid Message Number, interpreted as 0x20.

0x21-0x3FNot a valid Message Number, interpreted as 0x01-0x1F.

Note : When an invalid Message Number is written to the Command Request Register, the Message Number will be transformed into a valid value and that Message Object will be transferred.

3.3.3 IFx Message Buffer Registers

The bits of the Message Buffer registers mirror the Message Objects in the Message RAM. The function of the Message Objects bits is described in chapter 3.3.4.

3.3.3.1 IFx Mask Registers

IF1 Mask 1 Register

15

14

13

12 11 10 9 8 7 6 5 4 3 2 1 0

(addresses 0x15 & 0x14)

 

 

 

 

 

 

 

Msk15-0

 

 

 

 

 

IF1 Mask 2 Register

MXtd

MDir

res

Msk28-16

(addresses 0x17 & 0x16)

 

 

 

 

 

 

 

 

 

IF2 Mask 1 Register

 

 

 

Msk15-0

(addresses 0x45 & 0x44)

 

 

 

 

 

 

 

 

 

 

 

 

IF2 Mask 2 Register

MXtd

MDir

res

Msk28-16

(addresses 0x47 & 0x46)

 

 

 

 

rw

rw

r

rw

 

 

 

 

 

 

3.3.3.2 IFx Arbitration Registers

IF1 Arbitration 1 Register

15

14

13

12 11

10 9 8 7 6 5 4 3 2 1 0

(addresses 0x19 & 0x18)

 

 

 

 

 

 

 

 

 

ID15-0

 

 

 

 

 

 

IF1 Arbitration 2 Register

MsgVal

Xtd

Dir

 

ID28-16

(addresses 0x1B& 0x1A)

 

 

 

 

 

 

 

 

 

 

 

 

IF2 Arbitration 1 Register

 

 

 

 

ID15-0

(addresses 0x49 & 0x48)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

IF2 Arbitration 2 Register

MsgVal

Xtd

Dir

 

ID28-16

(addresses 0x4B & 0x4A)

 

 

 

 

 

rw

rw

rw

 

rw

 

 

 

 

 

 

 

 

BOSCH

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11.11.02

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Contents Robert Bosch GmbH User’s ManualCopyright Notice and Proprietary Information Conventions Scope References Terms and Abbreviations Functional Overview 2.2. Block Diagram Operating ModesChange Control Can Application List of Figures Ttcan ConfigurationTtcan Schedule Initialisation Ttcan Message HandlingHelvetica bold Change Control Current StatusChange History ConventionsTerm Meaning Functional Overview Ttcan CpuifcCan Message Transfer Operating Modes Software InitialisationTest Register addresses 0x0B & 0x0A Disabled Automatic RetransmissionTest Mode Ttcan =1 Loop Back combined with Silent Mode Loop Back ModeSoftware control of Pin Cantx No Message RAM ModeAddress Name Reset Value Ttcan Register Summary Hardware Reset DescriptionSIE CCEDAR EIEStatus Register addresses 0x03 No ErrorBit Timing Register addresses 0x07 Error Counter addresses 0x05Status Interrupts BRP Extension Register addresses 0x0D & 0x0C Arb IFx Command Mask RegistersDirection = Write ClrIntPnd IFx Command Request RegistersDirection = Read ControlIFx Mask Registers BusyMessage Number IFx Message Buffer RegistersMessage Object in the Message Memory IFx Message Control RegistersIFx Data a and Data B Registers Dir ID28-0Msk28-0 Xtd26/77 11.11.02 Interrupt Register addresses 0x09 Message Handler RegistersInterrupt Pending Registers Transmission Request RegistersNew Data Registers Trigger Number 2 IF1 Data B1 and B2 Registers for Trigger Memory AccessMessage Valid 1 Register MPr2-0 TT Operation Mode Register addresses 0x29Type TimeMark At CycleCount modTEW EecsRdlc AppWdL TT Interrupt Enable Register addresses 0x31CCM BarkSWE CELGTE GTWRTO TUR Numerator Configuration Low Register addresses 0x57 TT Error Level Register addresses 0x3F & 0x3ETT Cycle Count Register addresses 0x3D & 0x3C TT StopWatch Register addresses 0x61 TUR Denominator Configuration Register addresses 0x59TUR Numerator Actual Registers addresses 0x5B & 0x5A Egtf QCSQgtp EcalSWS TMCDET ECSTMG EPE40/77 11.11.02 Data Transfer Between IFx Registers and Message RAM Internal can Message HandlingStart Transmission of Messages in Event Driven can CommunicationStoring Received Messages in Fifo Buffers Acceptance Filtering of Received MessagesReception of Data Frame Reception of Remote FrameConfiguration of the Module Receive / Transmit PriorityCanclk input Nominal can Bit Time Sync PropSeg PhaseSeg1 PhaseSeg21 Configuration of the Bit Timing Bit Time and Bit RateBRP Propagation Time SegmentPhase Buffer Segments and Synchronisation Synchronisation on late and early Edges Filtering of Short Dominant Spikes 1.5 Configuration of the can Protocol Controller Oscillator Tolerance RangeCalculation of the Bit Timing Parameters Example for Bit Timing at high Baudrate 2 Configuration of the Message Memory Example for Bit Timing at low Baudrate2.2 Configuration of a Single Receive Object for Data Frames 2.1 Configuration of a Transmit Object for Data Frames2.3 Configuration of a Fifo Buffer Handling of Interrupts Can CommunicationUpdating a Transmit Object Reading from a Fifo Buffer Changing a Transmit ObjectReading Received Messages Requesting New Data for a Receive ObjectCPU Handling of a Fifo Buffer Interrupt Driven Ttcan Timing Ttcan ConfigurationMessage Scheduling TUR510 125000 32.5 100/12 529/17 Trigger Memory 63/77 11.11.02 Periodic Transmit Message Message ObjectsReference Message Potential Time Masters Event Driven Transmit MessageTime Slaves Event Driven Messages Ttcan Message Handling Message ReceptionMessage Transmission Periodic MessagesStopwatch Ttcan Gap ControlCycle Time and Global Time Synchronisation Previous RefMark Ttcan Interrupt and Error HandlingConfiguration Example Rdlc & TEW & CCM Register RemarkType & Msg & CycleCode RTO , TM , L2 , TTMode3 74/77 11.11.02 Customer Interface GenericInterface Interrupt Timing Timing of the Wait output signalCanclk Canwaitb Busy = ‘1’ Busy = ‘0’EOF
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