Bosch Appliances TTCAN user manual Ttcan Configuration, Ttcan Timing

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TTCAN

User’s Manual

Revision 1.6

5. TTCAN Application

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5.1 TTCAN Configuration

The TTCAN’s default operating mode after hardware reset is Standard CAN Communication without time triggers. The TTMode has to be switched into Configuration Mode before the timing and system matrix setup can be written into the TTCAN’s configuration registers. It is required that both Init and CCE are set before TTMode can be changed.

5.1.1 TTCAN Timing

The Network Time Unit (NTU) is the unit in which all times are measured. NTU is a constant of the whole network and is defined a priori by the network system designer. In TTCAN Level 1 NTU is the nominal CAN bit time. In TTCAN Level 2 NTU is a fraction of the physical second.

The length of the NTU is defined by the Time Unit Ratio, TUR. TUR is the ratio between the length of an NTU and the length of the FSE specific basic time unit, the system clock period. In the TTCAN, TUR = NumAct/DenomCfg is in principle a non-integer number. NTU is the time base for the Local Time, the integer part of Local Time (16-bit-value) will be incremented once each NTU. Cycle Time and Global Time are both derived from Local Time. The fractional part (3-bit-value) of Local Time, Cycle Time, and Global Time is not readable.

The default value of NumAct is NumCfg, but in nodes that are not the current time master, NumAct may be adapted during operation in a TTCAN Level 2 network. The default length of the NTU is given by the formula NTU = (NumCfg/DenomCfg) •System Clock Period or by the formula (NumCfg •System Clock Period) = (DenomCfg • NTU).

In a TTCAN Level 2 network, the nodes that are not the current time master will adapt their NumAct within a specified limit in order to compensate for clock drift between their local clock and the time master’s clock. The Synchronisation Deviation SD = NumCfg-NumActis

limited by the Synchronisation Deviation Limit SDL, which is configured by its dual logarithm ldSDL (SDL=2(ldSDL+5)) and should not exceed the clock tolerance given by the CAN bit

timing configuration. SD is calculated at each new Basic Cycle; when the calculated NumAct deviates by more than SDL from NumCfg, or if the Disc_Bit in the Reference Message is set, the drift compensation is suspended and the GTE interrupt is activated, or in case of the Disc_Bit the Dis interrupt is activated.

There is no drift compensation in TTCAN Level 1, NumAct will always be NumCfg.

The TUR Numerator Configuration NumCfg is an 18-bit number, its bits NumCfg[15…0] can be programmed in the range 0x0000-0xFFFF. NumCfg[17…16] is hard wired to 0b01, so when the number 0xnnnn is written to NumCfg[15…0] in the TUR Numerator Configuration Low register, NumAct starts with the value 0x10000+0x0nnnn = 0x1nnnn.

The TUR Denominator Configuration DenomCfg is a 14-bit number, 0x0000 is an illegal value for DenomCfg. DenomCfg[13…0] may be programmed in the range 0x0001-0x3FFF.

DenomCfg is set to 0x1000 and NumCfg is set to 0x10000 at hardware reset, resulting in an NTU consisting of 16 System Clock Periods. In Level 1, NumCfg must be ≥4•DenomCfg. In TTCAN Level 2, NumCfg must be ≥ 8 • DenomCfg to allow the 3-bit resolution for the internal fractional part of the NTU.

The clock calibration process in TTCAN Level 2 can adapt NumAct in the range of the Synchronisation Deviation Limit SDL [NumCfg-2(ldSDL+5)… NumCfg +2(ldSDL+5) ]. NumCfg should be programmed to the largest applicable numerical value in order to achieve the best accuracy in the calculation of NumAct. TUR configuration examples are shown in Figure 18.

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Contents User’s Manual Robert Bosch GmbHCopyright Notice and Proprietary Information Functional Overview 2.2. Block Diagram Operating Modes Change ControlConventions Scope References Terms and Abbreviations Can Application Ttcan Configuration Ttcan Schedule InitialisationTtcan Message Handling List of FiguresChange Control Current Status Change HistoryConventions Helvetica boldTerm Meaning Functional Overview Cpuifc TtcanOperating Modes Software Initialisation Can Message TransferDisabled Automatic Retransmission Test ModeTest Register addresses 0x0B & 0x0A Ttcan =1 Loop Back Mode Loop Back combined with Silent ModeNo Message RAM Mode Software control of Pin CantxAddress Name Reset Value Hardware Reset Description Ttcan Register SummaryCCE DAREIE SIENo Error Status Register addresses 0x03Error Counter addresses 0x05 Status InterruptsBit Timing Register addresses 0x07 BRP Extension Register addresses 0x0D & 0x0C IFx Command Mask Registers Direction = WriteArb IFx Command Request Registers Direction = ReadControl ClrIntPndBusy Message NumberIFx Message Buffer Registers IFx Mask RegistersIFx Message Control Registers IFx Data a and Data B RegistersMessage Object in the Message Memory ID28-0 Msk28-0Xtd Dir26/77 11.11.02 Message Handler Registers Interrupt Register addresses 0x09Transmission Request Registers New Data RegistersInterrupt Pending Registers 2 IF1 Data B1 and B2 Registers for Trigger Memory Access Message Valid 1 RegisterTrigger Number TT Operation Mode Register addresses 0x29 TypeTimeMark At CycleCount mod MPr2-0Eecs RdlcTEW TT Interrupt Enable Register addresses 0x31 CCMBark AppWdLCEL GTEGTW SWERTO TT Error Level Register addresses 0x3F & 0x3E TT Cycle Count Register addresses 0x3D & 0x3CTUR Numerator Configuration Low Register addresses 0x57 TUR Denominator Configuration Register addresses 0x59 TUR Numerator Actual Registers addresses 0x5B & 0x5ATT StopWatch Register addresses 0x61 QCS QgtpEcal EgtfTMC DETECS SWSEPE TMG40/77 11.11.02 Internal can Message Handling Data Transfer Between IFx Registers and Message RAMTransmission of Messages in Event Driven can Communication StartAcceptance Filtering of Received Messages Reception of Data FrameReception of Remote Frame Storing Received Messages in Fifo BuffersReceive / Transmit Priority Configuration of the ModuleSync PropSeg PhaseSeg1 PhaseSeg2 1 Configuration of the Bit TimingBit Time and Bit Rate Canclk input Nominal can Bit TimePropagation Time Segment BRPPhase Buffer Segments and Synchronisation Synchronisation on late and early Edges Filtering of Short Dominant Spikes Oscillator Tolerance Range 1.5 Configuration of the can Protocol ControllerCalculation of the Bit Timing Parameters Example for Bit Timing at high Baudrate Example for Bit Timing at low Baudrate 2 Configuration of the Message Memory2.1 Configuration of a Transmit Object for Data Frames 2.2 Configuration of a Single Receive Object for Data Frames2.3 Configuration of a Fifo Buffer Can Communication Handling of InterruptsUpdating a Transmit Object Changing a Transmit Object Reading Received MessagesRequesting New Data for a Receive Object Reading from a Fifo BufferCPU Handling of a Fifo Buffer Interrupt Driven Ttcan Configuration Ttcan TimingTUR 510 125000 32.5 100/12 529/17Message Scheduling Trigger Memory 63/77 11.11.02 Message Objects Reference MessagePeriodic Transmit Message Event Driven Transmit Message Time SlavesPotential Time Masters Ttcan Message Handling Message Reception Message TransmissionPeriodic Messages Event Driven MessagesTtcan Gap Control StopwatchCycle Time and Global Time Synchronisation Ttcan Interrupt and Error Handling Previous RefMarkConfiguration Example Register Remark Rdlc & TEW & CCMType & Msg & CycleCode RTO , TM , L2 , TTMode3 74/77 11.11.02 Generic InterfaceCustomer Interface Timing of the Wait output signal Canclk CanwaitbBusy = ‘1’ Busy = ‘0’ Interrupt TimingEOF
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