Bosch Appliances TTCAN user manual Example for Bit Timing at low Baudrate

Page 53

TTCAN

User’s Manual

Revision 1.6

4.2.1.8 Example for Bit Timing at low Baudrate

In this example, the frequency of CAN_CLK is 2 MHz, BRP is 1, the bit rate is 100 KBit/s.

tq

1

∝s

delay of bus driver

200

ns

delay of receiver circuit

80

ns

delay of bus line (40m)

220

ns

tProp

1

∝s

tSJW

4

∝s

tTSeg1

5

∝s

tTSeg2

4

∝s

tSync-Seg

1

∝s

bit time

10

∝s

tolerance for CAN_CLK

1.58

%

 

 

=

= 2 • tCAN_CLK

= 1 • tq = 4 • tq

= tProp + tSJW

= Information Processing Time + 3 • tq = 1 • tq

= tSync-Seg + tTSeg1 + tTSeg2

= min(PB 1, PB 2)

----------------------------------------------------------------

2 × (13 × bit time –PB2)

4µs

---------------------------------------------------------

2 × (13 × 10µs –4µs)

manual_about.fm

In this example, the concatenated bit time parameters are (4-1)3&(5-1)4&(4-1)2&(2-1)6, the Bit Timing Register is programmed to= 0x34C1.

4.2.2 Configuration of the Message Memory

The whole Message Memory has to be configured before the end of the initialisation, but is also possible to change the configuration of Message Objects during CAN communication.

The CAN software driver library should offer subroutines that:

•Transfer a complete message structure into a Message Object. (Configuration)

•Transfer the data bytes of a message into a Message Object and set TxRqst and NewDat. (Start a new transmission)

•Get the data bytes of a message from a Message Object and clear NewDat (and IntPnd). (Read received data)

•Get the complete message from a Message Object and clear NewDat (and IntPnd). (Read a received message, including identifier, from a Message Object with UMask = ‘1’)

Parameters of the subroutines are the Message Number and a pointer to a complete message structure or to the data bytes of a message structure.

Two methods are possible to assign the IFx Interface Register sets to these subroutines. In the first method, the tasks of the application program that may access the module are assorted in two groups. Each group is restricted to the use of one of the Interface Register sets. The tasks of one group may interrupt tasks of the other group, but not of the same group.

In the second method, which may be a special case of the first method, there are only two tasks is the application program that access the module. A Read_Message task that uses IFC1 to get received messages (full messages or data bytes only) from the Message RAM and a Write_Message task that uses IFC2 to write messages to be transmitted (or to be configured) into the Message RAM. Both tasks may interrupt each other.

The CAN communication may be controlled interrupt-driven or by polling. The module’s Interrupt Register points to Message Objects with IntPnd = ‘1’. It is updated even if the interrupt line to the CPU is disabled (IE = ‘0’).

BOSCH

- 53/77 -

11.11.02

Page 52 Page 54
Image 53
Page 52 Page 54
Contents Robert Bosch GmbH User’s ManualCopyright Notice and Proprietary Information Conventions Scope References Terms and Abbreviations Functional Overview 2.2. Block Diagram Operating ModesChange Control Can Application Ttcan Schedule Initialisation Ttcan ConfigurationTtcan Message Handling List of FiguresChange History Change Control Current StatusConventions Helvetica boldTerm Meaning Functional Overview Ttcan CpuifcCan Message Transfer Operating Modes Software InitialisationTest Register addresses 0x0B & 0x0A Disabled Automatic RetransmissionTest Mode Ttcan =1 Loop Back combined with Silent Mode Loop Back ModeSoftware control of Pin Cantx No Message RAM ModeAddress Name Reset Value Ttcan Register Summary Hardware Reset DescriptionDAR CCEEIE SIEStatus Register addresses 0x03 No ErrorBit Timing Register addresses 0x07 Error Counter addresses 0x05Status Interrupts BRP Extension Register addresses 0x0D & 0x0C Arb IFx Command Mask RegistersDirection = Write Direction = Read IFx Command Request RegistersControl ClrIntPndMessage Number BusyIFx Message Buffer Registers IFx Mask RegistersMessage Object in the Message Memory IFx Message Control RegistersIFx Data a and Data B Registers Msk28-0 ID28-0Xtd Dir26/77 11.11.02 Interrupt Register addresses 0x09 Message Handler RegistersInterrupt Pending Registers Transmission Request RegistersNew Data Registers Trigger Number 2 IF1 Data B1 and B2 Registers for Trigger Memory AccessMessage Valid 1 Register Type TT Operation Mode Register addresses 0x29TimeMark At CycleCount mod MPr2-0TEW EecsRdlc CCM TT Interrupt Enable Register addresses 0x31Bark AppWdLGTE CELGTW SWERTO TUR Numerator Configuration Low Register addresses 0x57 TT Error Level Register addresses 0x3F & 0x3ETT Cycle Count Register addresses 0x3D & 0x3C TT StopWatch Register addresses 0x61 TUR Denominator Configuration Register addresses 0x59TUR Numerator Actual Registers addresses 0x5B & 0x5A Qgtp QCSEcal EgtfDET TMCECS SWSTMG EPE40/77 11.11.02 Data Transfer Between IFx Registers and Message RAM Internal can Message HandlingStart Transmission of Messages in Event Driven can CommunicationReception of Data Frame Acceptance Filtering of Received MessagesReception of Remote Frame Storing Received Messages in Fifo BuffersConfiguration of the Module Receive / Transmit Priority1 Configuration of the Bit Timing Sync PropSeg PhaseSeg1 PhaseSeg2Bit Time and Bit Rate Canclk input Nominal can Bit TimeBRP Propagation Time SegmentPhase Buffer Segments and Synchronisation Synchronisation on late and early Edges Filtering of Short Dominant Spikes 1.5 Configuration of the can Protocol Controller Oscillator Tolerance RangeCalculation of the Bit Timing Parameters Example for Bit Timing at high Baudrate 2 Configuration of the Message Memory Example for Bit Timing at low Baudrate2.2 Configuration of a Single Receive Object for Data Frames 2.1 Configuration of a Transmit Object for Data Frames2.3 Configuration of a Fifo Buffer Handling of Interrupts Can CommunicationUpdating a Transmit Object Reading Received Messages Changing a Transmit ObjectRequesting New Data for a Receive Object Reading from a Fifo BufferCPU Handling of a Fifo Buffer Interrupt Driven Ttcan Timing Ttcan ConfigurationMessage Scheduling TUR510 125000 32.5 100/12 529/17 Trigger Memory 63/77 11.11.02 Periodic Transmit Message Message ObjectsReference Message Potential Time Masters Event Driven Transmit MessageTime Slaves Message Transmission Ttcan Message Handling Message ReceptionPeriodic Messages Event Driven MessagesStopwatch Ttcan Gap ControlCycle Time and Global Time Synchronisation Previous RefMark Ttcan Interrupt and Error HandlingConfiguration Example Rdlc & TEW & CCM Register RemarkType & Msg & CycleCode RTO , TM , L2 , TTMode3 74/77 11.11.02 Customer Interface GenericInterface Canclk Canwaitb Timing of the Wait output signalBusy = ‘1’ Busy = ‘0’ Interrupt TimingEOF
Top Page Image Contents