Bosch Appliances TTCAN user manual Message Valid 1 Register, Trigger Number

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TTCAN

User’s Manual

Revision 1.6

manual_about.fm

3.4.5 Message Valid 1 Register

Message Valid 1 Register	15 14 13 12 11 10 9 8	7	6 5 4 3 2 1 0
(addresses 0xB1 & 0xB0)
(addresses 0xB1 & 0xB0)	MsgVal16-9		MsgVal8-1

Message Valid 2 Register	MsgVal32-25		MsgVal24-17
(addresses 0xB3 & 0xB2)
(addresses 0xB3 & 0xB2)	r		r
	r		r

MsgVal32-1Message Valid Bits (of all Message Objects)

one This Message Object is conﬁgured and should be considered by the Mes- sage Handler.

zero This Message Object is ignored by the Message Handler.

These registers hold the MsgVal bits of the 32 Message Objects. By reading out the MsgVal bits, the CPU can check which Message Object is valid. The MsgVal bit of a speciﬁc Message Object can be set/reset by the CPU via the IFx Message Interface Registers.

3.5Registers for Time Triggered Communication

3.5.1Trigger Memory Access Register (addresses 0x0F & 0x0E)

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Rd/Wr	res	res	res	res	res	res	res	res	res	res		Trigger Number

rw	r	r	r	r	r	r	r	r	r	r			rw

Rd/Wr Read / Write

one Write to selected Trigger. zero Read from selected Trigger.

Trigger Number

0x00-0x1FThe trigger is selected for data transfer between Trigger Memory and IF1 Message Data B1 and B2 Registers.

Note : The CPU may access the Trigger Memory only during Conﬁguration Mode. During active mode, the write to the Trigger Memory Access register is locked. The Trigger Memory access is started by a write to the low byte of the Trigger Memory Access register.

3.5.2 IF1 Data B1 and B2 Registers for Trigger Memory Access

The trigger data of the TTCAN system matrix is stored in the Trigger Memory. The Trigger Memory is accessed via the IF1 Data B1 and B2 Registers. The data transfer is controlled by the Trigger Memory Access Register. The bits of IF1 Data B1 and B2 Registers correspond with the bits of a Trigger Memory word according to the following table :

	15	14	13	12	11	10	9	8	7		6	5	4		3	2	1	0

IF1 Message Data B1		Type			Message Number				res				Cycle_Code

IF1 Message Data B2								Time_Mark

					rw									rw

Note : Accesses to the Trigger Memory are controlled by the Trigger Memory Access Register, which selects a word of the Trigger Memory and speciﬁes the direction of the data transfer.

On each transfer, 32 bits are loaded either from the IF1 Data B1 and B2 Registers to the selected Trigger Memory word or vice versa.

BOSCH

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Contents Robert Bosch GmbH User’s ManualCopyright Notice and Proprietary Information Conventions Scope References Terms and Abbreviations Functional Overview 2.2. Block Diagram Operating ModesChange Control Can Application Ttcan Schedule Initialisation Ttcan ConfigurationTtcan Message Handling List of FiguresChange History Change Control Current StatusConventions Helvetica boldTerm Meaning Functional Overview Ttcan CpuifcCan Message Transfer Operating Modes Software InitialisationTest Register addresses 0x0B & 0x0A Disabled Automatic RetransmissionTest Mode Ttcan =1 Loop Back combined with Silent Mode Loop Back ModeSoftware control of Pin Cantx No Message RAM ModeAddress Name Reset Value Ttcan Register Summary Hardware Reset DescriptionDAR CCEEIE SIEStatus Register addresses 0x03 No ErrorBit Timing Register addresses 0x07 Error Counter addresses 0x05Status Interrupts BRP Extension Register addresses 0x0D & 0x0C Arb IFx Command Mask RegistersDirection = Write Direction = Read IFx Command Request RegistersControl ClrIntPndMessage Number BusyIFx Message Buffer Registers IFx Mask RegistersMessage Object in the Message Memory IFx Message Control RegistersIFx Data a and Data B Registers Msk28-0 ID28-0Xtd Dir26/77 11.11.02 Interrupt Register addresses 0x09 Message Handler RegistersInterrupt Pending Registers Transmission Request RegistersNew Data Registers Trigger Number 2 IF1 Data B1 and B2 Registers for Trigger Memory AccessMessage Valid 1 Register Type TT Operation Mode Register addresses 0x29TimeMark At CycleCount mod MPr2-0TEW EecsRdlc CCM TT Interrupt Enable Register addresses 0x31Bark AppWdLGTE CELGTW SWERTO TUR Numerator Conﬁguration Low Register addresses 0x57 TT Error Level Register addresses 0x3F & 0x3ETT Cycle Count Register addresses 0x3D & 0x3C TT StopWatch Register addresses 0x61 TUR Denominator Conﬁguration Register addresses 0x59TUR Numerator Actual Registers addresses 0x5B & 0x5A Qgtp QCSEcal EgtfDET TMCECS SWSTMG EPE40/77 11.11.02 Data Transfer Between IFx Registers and Message RAM Internal can Message HandlingStart Transmission of Messages in Event Driven can CommunicationReception of Data Frame Acceptance Filtering of Received MessagesReception of Remote Frame Storing Received Messages in Fifo BuffersConﬁguration of the Module Receive / Transmit Priority1 Conﬁguration of the Bit Timing Sync PropSeg PhaseSeg1 PhaseSeg2Bit Time and Bit Rate Canclk input Nominal can Bit TimeBRP Propagation Time SegmentPhase Buffer Segments and Synchronisation Synchronisation on late and early Edges Filtering of Short Dominant Spikes 1.5 Conﬁguration of the can Protocol Controller Oscillator Tolerance RangeCalculation of the Bit Timing Parameters Example for Bit Timing at high Baudrate 2 Conﬁguration of the Message Memory Example for Bit Timing at low Baudrate2.2 Conﬁguration of a Single Receive Object for Data Frames 2.1 Conﬁguration of a Transmit Object for Data Frames2.3 Conﬁguration of a Fifo Buffer Handling of Interrupts Can CommunicationUpdating a Transmit Object Reading Received Messages Changing a Transmit ObjectRequesting New Data for a Receive Object Reading from a Fifo BufferCPU Handling of a Fifo Buffer Interrupt Driven Ttcan Timing Ttcan ConﬁgurationMessage Scheduling TUR510 125000 32.5 100/12 529/17 Trigger Memory 63/77 11.11.02 Periodic Transmit Message Message ObjectsReference Message Potential Time Masters Event Driven Transmit MessageTime Slaves Message Transmission Ttcan Message Handling Message ReceptionPeriodic Messages Event Driven MessagesStopwatch Ttcan Gap ControlCycle Time and Global Time Synchronisation Previous RefMark Ttcan Interrupt and Error HandlingConﬁguration Example Rdlc & TEW & CCM Register RemarkType & Msg & CycleCode RTO , TM , L2 , TTMode3 74/77 11.11.02 Customer Interface GenericInterface Canclk Canwaitb Timing of the Wait output signalBusy = ‘1’ Busy = ‘0’ Interrupt TimingEOF