Bosch Appliances TTCAN user manual Register Remark, Rdlc & TEW & CCM

Page 71

TTCAN

User’s Manual

Revision 1.6

The general conﬁguration of the three nodes is identical, there are differences in the Operation Mode, the TT Matrix Limits, the Message RAM, and the Trigger Memory. Note that the CPU has to wait after each write access to the IF1 Command Request Register for the requested transfer to be completed (check of Busy bit).

	Line	Ad	Register	Remark	M0	M1	S0


	1	00	CAN Control	enable conﬁguration		0041

	2	02	CAN Status	read register to check reason for (re-?)conﬁguration

	3	02	CAN Status	clear LEC		0007

	4	06	Bit Timing	bit time = 10 tq = 1 ∝s		1640

	5	0C	BRP Extension	1 tq=clock period = 100 ns		0000

	6	28	TT Operation Mode	conﬁguration mode		0001

	7	66	TT Clock Control	disable clock functions		0000

	8	2A	TT Matrix Limits1	Tx_Triggers in Matrix Cycle	0009	000A	000B

	9	2C	TT Matrix Limits2	RDLC & TEW & CCM		4703

	10	2E	TT Application Watchdog Limit	limit=0xFF00NTU =65ms		00FF

	11	30	TT Interrupt Enable	enable error interrupts		F000

	12	32	TT Interrupt Vector	clear all interrupts		0000

	13	56	TUR-NumeratorCfg	0x1FFFE clock periods =		FFFE
				0x3333 NTU; NTU = 1 ∝s
	14	58	TUR-DenominatorCfg	0x3333 NTU; NTU = 1 ∝s		3333

	15	6C	TT Time Mark	generate TMI at Time Mark	0100	0200	0300

	16	6E	TT Gap Control	disable gap functions		0000

	17	12	IF1 Command Mask	write Mask, Arb, Control, Data		00F3

	18	14	IF1 Mask1	3 LSB of 11-bit Reference Mes-		FFFF
				sage identiﬁer masked
	19	16	IF1 Mask2	sage identiﬁer masked	9FE3		DFE3

	20	18	IF1 Arbitration1	MsgVal, 11-bit id, Dir =Tx/Rx,		0000
				Ref_Msg identiﬁer=0F0
	21	1A	IF1 Arbitration2	Ref_Msg identiﬁer=0F0	A3C0		83C0

	22	1C	IF1 Message Control	NewDat, UMask, EoB, DLC=4		9084

	23	1E	IF1 Message Data A1			FACE

	24	20	IF1 Message Data A2	some bytes for initialisation		B055

about.fm	25	22	IF1 Message Data B1			FEED
	25	22	IF1 Message Data B1			FEED

	26	24	IF1 Message Data B2			CAFE
_
manual	27	10	IF1 Command Request	Ref_Msg in message object 1		0001
	27	10	IF1 Command Request	Ref_Msg in message object 1		0001

	28	16	IF1 Mask2	all bits must match		FFFF

	29	1A	IF1 Arbitration2	MsgVal, Dir =Tx, xx_Msg2 id	AC08	AC48	AC88

	30	1C	IF1 Message Control	NewDat, EoB, DLC=8		8088

	31	10	IF1 Command Request	xx_Msg2 in message object 2		0002

	32	1A	IF1 Arbitration2	MsgVal, Dir =Tx, xx_Msg3 id	AC0C	AC4C	AC8C

	33	10	IF1 Command Request	xx_Msg3 in message object 3		0003

	34	1A	IF1 Arbitration2	MsgVal, Dir =Tx, M1_Msg4 id	0000	AC50	0000

	35	10	IF1 Command Request	M1_Msg4 in message object 4		0004

	36	1A	IF1 Arbitration2	not valid, Dir =Tx, dummy id		4FFF

BOSCH

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11.11.02

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Contents Robert Bosch GmbH User’s ManualCopyright Notice and Proprietary Information Conventions Scope References Terms and Abbreviations Functional Overview 2.2. Block Diagram Operating ModesChange Control Can Application List of Figures Ttcan ConfigurationTtcan Schedule Initialisation Ttcan Message HandlingHelvetica bold Change Control Current StatusChange History ConventionsTerm Meaning Functional Overview Ttcan CpuifcCan Message Transfer Operating Modes Software InitialisationTest Register addresses 0x0B & 0x0A Disabled Automatic RetransmissionTest Mode Ttcan =1 Loop Back combined with Silent Mode Loop Back ModeSoftware control of Pin Cantx No Message RAM ModeAddress Name Reset Value Ttcan Register Summary Hardware Reset DescriptionSIE CCEDAR EIEStatus Register addresses 0x03 No ErrorBit Timing Register addresses 0x07 Error Counter addresses 0x05Status Interrupts BRP Extension Register addresses 0x0D & 0x0C Arb IFx Command Mask RegistersDirection = Write ClrIntPnd IFx Command Request RegistersDirection = Read ControlIFx Mask Registers BusyMessage Number IFx Message Buffer RegistersMessage Object in the Message Memory IFx Message Control RegistersIFx Data a and Data B Registers Dir ID28-0Msk28-0 Xtd26/77 11.11.02 Interrupt Register addresses 0x09 Message Handler RegistersInterrupt Pending Registers Transmission Request RegistersNew Data Registers Trigger Number 2 IF1 Data B1 and B2 Registers for Trigger Memory AccessMessage Valid 1 Register MPr2-0 TT Operation Mode Register addresses 0x29Type TimeMark At CycleCount modTEW EecsRdlc AppWdL TT Interrupt Enable Register addresses 0x31CCM BarkSWE CELGTE GTWRTO TUR Numerator Conﬁguration Low Register addresses 0x57 TT Error Level Register addresses 0x3F & 0x3ETT Cycle Count Register addresses 0x3D & 0x3C TT StopWatch Register addresses 0x61 TUR Denominator Conﬁguration Register addresses 0x59TUR Numerator Actual Registers addresses 0x5B & 0x5A Egtf QCSQgtp EcalSWS TMCDET ECSTMG EPE40/77 11.11.02 Data Transfer Between IFx Registers and Message RAM Internal can Message HandlingStart Transmission of Messages in Event Driven can CommunicationStoring Received Messages in Fifo Buffers Acceptance Filtering of Received MessagesReception of Data Frame Reception of Remote FrameConﬁguration of the Module Receive / Transmit PriorityCanclk input Nominal can Bit Time Sync PropSeg PhaseSeg1 PhaseSeg21 Conﬁguration of the Bit Timing Bit Time and Bit RateBRP Propagation Time SegmentPhase Buffer Segments and Synchronisation Synchronisation on late and early Edges Filtering of Short Dominant Spikes 1.5 Conﬁguration of the can Protocol Controller Oscillator Tolerance RangeCalculation of the Bit Timing Parameters Example for Bit Timing at high Baudrate 2 Conﬁguration of the Message Memory Example for Bit Timing at low Baudrate2.2 Conﬁguration of a Single Receive Object for Data Frames 2.1 Conﬁguration of a Transmit Object for Data Frames2.3 Conﬁguration of a Fifo Buffer Handling of Interrupts Can CommunicationUpdating a Transmit Object Reading from a Fifo Buffer Changing a Transmit ObjectReading Received Messages Requesting New Data for a Receive ObjectCPU Handling of a Fifo Buffer Interrupt Driven Ttcan Timing Ttcan ConﬁgurationMessage Scheduling TUR510 125000 32.5 100/12 529/17 Trigger Memory 63/77 11.11.02 Periodic Transmit Message Message ObjectsReference Message Potential Time Masters Event Driven Transmit MessageTime Slaves Event Driven Messages Ttcan Message Handling Message ReceptionMessage Transmission Periodic MessagesStopwatch Ttcan Gap ControlCycle Time and Global Time Synchronisation Previous RefMark Ttcan Interrupt and Error HandlingConﬁguration Example Rdlc & TEW & CCM Register RemarkType & Msg & CycleCode RTO , TM , L2 , TTMode3 74/77 11.11.02 Customer Interface GenericInterface Interrupt Timing Timing of the Wait output signalCanclk Canwaitb Busy = ‘1’ Busy = ‘0’EOF