Bosch Appliances TTCAN user manual Software control of Pin Cantx, No Message RAM Mode

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TTCAN

User’s Manual

Revision 1.6

manual_about.fm

2.3.4.6 Software control of Pin CAN_TX

Four output functions are available for the CAN transmit pin CAN_TX. Additionally to its default function – the serial data output – it can drive the CAN Sample Point signal to monitor the CAN_Core’s bit timing and it can drive constant dominant or recessive values. The last two functions, combined with the readable CAN receive pin CAN_RX, can be used to check the CAN bus’ physical layer.

The output mode of pin CAN_TX is selected by programming the Test Register bits Tx1 and Tx0 as described in section 2.3.4.1 on page 11.

The three test functions for pin CAN_TX interfere with all CAN protocol functions. CAN_TX must be left in its default function when CAN message transfer or any of the test modes Loop Back Mode, Silent Mode, or No Message RAM Mode are selected.

2.3.4.7 No Message RAM Mode

The CAN_Core can be set in No Message RAM Mode by programming the Test Register bit NoRAM to one. In this mode the TTCAN module operates without the Message RAM.

The IF1 Registers are used as Transmit Buffer. The transmission of the contents of the IF1 Registers is requested by writing the Busy bit of the IF1 Command Request Register to ‘1’. The IF1 Registers are locked while the Busy bit is set. The Busy bit indicates that the transmission is pending. The CPU-IFC’s output signal CAN_WAIT_B is disabled (always ‘1’) in this mode.

As soon the CAN bus is idle, the IF1 Registers are loaded into the CAN_Core’s shift register and the transmission is started. When the transmission has completed, the Busy bit is reset and the locked IF1 Registers are released.

A pending transmission can be aborted at any time by resetting the Busy bit in the IF1 Command Request Register while the IF1 Registers are locked. If the CPU has reset the Busy bit, a possible retransmission in case of lost arbitration or in case of an error is disabled.

The IF2 Registers are used as Receive Buffer. After the reception of a message the contents of the shift register is stored into the IF2 Registers, without any acceptance filtering.

Additionally, the actual contents of the shift register can be monitored during the message transfer. Each time a read Message Object is initiated by writing the Busy bit of the IF2 Command Request Register to ‘1’, the contents of the shift register is stored into the IF2 Registers.

In No Message RAM Mode the evaluation of all Message Object related control and status bits and of the control bits of the IFx Command Mask Registers is turned off. The message number of the Command request registers is not evaluated. The NewDat and MsgLst bits of the IF2 Message Control Register retain their function, DLC3-0will show the received DLC, the other control bits will be read as ‘0’.

The No Message RAM Mode is a hardware test mode that allows to evaluate the TTCAN IP RTL code in FPGA types that do not support the TTCAN’s Message RAM structure.

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Contents User’s Manual Robert Bosch GmbHCopyright Notice and Proprietary Information Conventions Scope References Terms and Abbreviations Functional Overview 2.2. Block Diagram Operating ModesChange Control Can Application Ttcan Message Handling Ttcan ConfigurationTtcan Schedule Initialisation List of FiguresConventions Change Control Current StatusChange History Helvetica boldTerm Meaning Functional Overview Cpuifc TtcanOperating Modes Software Initialisation Can Message TransferTest Register addresses 0x0B & 0x0A Disabled Automatic RetransmissionTest Mode Ttcan =1 Loop Back Mode Loop Back combined with Silent ModeNo Message RAM Mode Software control of Pin CantxAddress Name Reset Value Hardware Reset Description Ttcan Register SummaryEIE CCEDAR SIENo Error Status Register addresses 0x03Bit Timing Register addresses 0x07 Error Counter addresses 0x05Status Interrupts BRP Extension Register addresses 0x0D & 0x0C Arb IFx Command Mask RegistersDirection = Write Control IFx Command Request RegistersDirection = Read ClrIntPndIFx Message Buffer Registers BusyMessage Number IFx Mask RegistersMessage Object in the Message Memory IFx Message Control RegistersIFx Data a and Data B Registers Xtd ID28-0Msk28-0 Dir26/77 11.11.02 Message Handler Registers Interrupt Register addresses 0x09Interrupt Pending Registers Transmission Request RegistersNew Data Registers Trigger Number 2 IF1 Data B1 and B2 Registers for Trigger Memory AccessMessage Valid 1 Register TimeMark At CycleCount mod TT Operation Mode Register addresses 0x29Type MPr2-0TEW EecsRdlc Bark TT Interrupt Enable Register addresses 0x31CCM AppWdLGTW CELGTE SWERTO TUR Numerator Configuration Low Register addresses 0x57 TT Error Level Register addresses 0x3F & 0x3ETT Cycle Count Register addresses 0x3D & 0x3C TT StopWatch Register addresses 0x61 TUR Denominator Configuration Register addresses 0x59TUR Numerator Actual Registers addresses 0x5B & 0x5A Ecal QCSQgtp EgtfECS TMCDET SWSEPE TMG40/77 11.11.02 Internal can Message Handling Data Transfer Between IFx Registers and Message RAMTransmission of Messages in Event Driven can Communication StartReception of Remote Frame Acceptance Filtering of Received MessagesReception of Data Frame Storing Received Messages in Fifo BuffersReceive / Transmit Priority Configuration of the ModuleBit Time and Bit Rate Sync PropSeg PhaseSeg1 PhaseSeg21 Configuration of the Bit Timing Canclk input Nominal can Bit TimePropagation Time Segment BRPPhase Buffer Segments and Synchronisation Synchronisation on late and early Edges Filtering of Short Dominant Spikes Oscillator Tolerance Range 1.5 Configuration of the can Protocol ControllerCalculation of the Bit Timing Parameters Example for Bit Timing at high Baudrate Example for Bit Timing at low Baudrate 2 Configuration of the Message Memory2.1 Configuration of a Transmit Object for Data Frames 2.2 Configuration of a Single Receive Object for Data Frames2.3 Configuration of a Fifo Buffer Can Communication Handling of InterruptsUpdating a Transmit Object Requesting New Data for a Receive Object Changing a Transmit ObjectReading Received Messages Reading from a Fifo BufferCPU Handling of a Fifo Buffer Interrupt Driven Ttcan Configuration Ttcan TimingMessage Scheduling TUR510 125000 32.5 100/12 529/17 Trigger Memory 63/77 11.11.02 Periodic Transmit Message Message ObjectsReference Message Potential Time Masters Event Driven Transmit MessageTime Slaves Periodic Messages Ttcan Message Handling Message ReceptionMessage Transmission Event Driven MessagesTtcan Gap Control StopwatchCycle Time and Global Time Synchronisation Ttcan Interrupt and Error Handling Previous RefMarkConfiguration Example Register Remark Rdlc & TEW & CCMType & Msg & CycleCode RTO , TM , L2 , TTMode3 74/77 11.11.02 Customer Interface GenericInterface Busy = ‘1’ Busy = ‘0’ Timing of the Wait output signalCanclk Canwaitb Interrupt TimingEOF
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