Bosch Appliances TTCAN user manual Trigger Memory

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TTCAN

User’s Manual

Revision 1.6

manual_about.fm

operates according to ISO 11898-4, but without the possibility to synchronise the Basic Cycles to external events, the Next_is_Gap bit in the Reference Message is ignored. In the TTMode “Event Synchronised Time Triggered Operation”, the TTCAN module operates according to ISO 11898-4, including the event synchronised start of a Basic Cycle.

ETT in the Matrix Limits registers specifies the number of Expected Tx_Triggers in the System Matrix. This is the sum of the Tx_Triggers for Exclusive, single Arbitrating and Merged Arbitrating Windows, excluding the Tx_Ref_Triggers. Note that this is usually not the number of Tx_Triggers in the Trigger Memory; the number of Basic Cycles in the System Matrix and the Trigger’s Repeat Factors have to be taken into account. An inaccurate configuration of ETT will result in either a Tx_Underflow (Error level 1) or in a Tx_Overflow (Error level 2).

CCM specifies the number of the last Basic Cycle in the System Matrix. The counting of Basic Cycles starts at 0, so in a System Matrix consisting of 8 Basic Cycles CCM would be 7. CCM is ignored by Time Slaves, a receiver of a Reference Message considers the received Cycle_Count as the valid Cycle_Count for the actual Basic Cycle.

RDLC specifies the Data Length Code of the Reference Messages transmitted by a potential Time Master. It has to be at least 0x1 for TTCAN Level 1 and 0x4 for TTCAN Level 2.

TEW specifies the length of the Tx_Enable Window in NTUs. The Tx_Enable Window is that period of time at the beginning of a Time Window where a transmission may be started. If a transmission of a message cannot be started inside the Tx_Enable Window, because of e.g. a slight overlap from the previous Time Window’s message, the transmission cannot be started in that Time Window at all. TEW has to be chosen with respect to the network’s synchronisation quality and with respect to the relation between the length of the Time Windows and the length of the messages.

Which interrupt sources to enable in the TT Interrupt Enable register is application specific. Write accesses to the Interrupt Enable register are not restricted to the Configuration Mode.

5.1.3 Trigger Memory

The Trigger Memory holds place for up to 32 Triggers. The Trigger information consists of Time_Mark, Message Number, Cycle_Code, and Trigger Type.

The Time_Mark defines at which Cycle Time a the Trigger becomes active.

Message Number and Cycle_Code are defined for all Triggers, but they are ignored for the Trigger Types Tx_Ref_Trigger, Tx_Ref_Trigger_Gap, Watch_Trigger, Watch_Trigger_Gap, and EndOfList. The Reference Message is linked to Message Object Number 1 by hardware and neither the Watch_Triggers nor the EndOfList Trigger are linked to any Message Object.

Eight different Trigger Types are available :

Tx_Ref_Trigger and Tx_Ref_Trigger_Gap cause the transmission of a Reference Message by a Time Master. A Configuration Error (Error level 3) is detected when a Time Slave encounters a Tx_Ref_Trigger(_Gap) in its Trigger Memory. Tx_Ref_Trigger_Gap is only used for the Event Synchronised Time Triggered Operation mode. In that mode, Tx_Ref_Trigger is ignored when the TTCAN Synchronisation State SyncSt is In_Gap.

Watch_Trigger and Watch_Trigger_Gap check for missing Reference Messages. They are used by both Time Masters and Time Slaves. Watch_Trigger_Gap is only used for the Event Synchronised Time Triggered Operation mode. In that mode, Watch_Trigger is ignored when the TTCAN Synchronisation State SyncSt is In_Gap.

Tx_Trigger_Single and Tx_Trigger_Merged both cause the start of a transmission, they define the start of Time Windows. Tx_Trigger_Single may be used for Exclusive Time Windows and

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Contents User’s Manual Robert Bosch GmbHCopyright Notice and Proprietary Information Conventions Scope References Terms and Abbreviations Functional Overview 2.2. Block Diagram Operating ModesChange Control Can Application Ttcan Message Handling Ttcan ConfigurationTtcan Schedule Initialisation List of FiguresConventions Change Control Current StatusChange History Helvetica boldTerm Meaning Functional Overview Cpuifc TtcanOperating Modes Software Initialisation Can Message TransferTest Register addresses 0x0B & 0x0A Disabled Automatic RetransmissionTest Mode Ttcan =1 Loop Back Mode Loop Back combined with Silent ModeNo Message RAM Mode Software control of Pin CantxAddress Name Reset Value Hardware Reset Description Ttcan Register SummaryEIE CCEDAR SIENo Error Status Register addresses 0x03Bit Timing Register addresses 0x07 Error Counter addresses 0x05Status Interrupts BRP Extension Register addresses 0x0D & 0x0C Arb IFx Command Mask RegistersDirection = Write Control IFx Command Request RegistersDirection = Read ClrIntPndIFx Message Buffer Registers BusyMessage Number IFx Mask RegistersMessage Object in the Message Memory IFx Message Control RegistersIFx Data a and Data B Registers Xtd ID28-0Msk28-0 Dir26/77 11.11.02 Message Handler Registers Interrupt Register addresses 0x09Interrupt Pending Registers Transmission Request RegistersNew Data Registers Trigger Number 2 IF1 Data B1 and B2 Registers for Trigger Memory AccessMessage Valid 1 Register TimeMark At CycleCount mod TT Operation Mode Register addresses 0x29Type MPr2-0TEW EecsRdlc Bark TT Interrupt Enable Register addresses 0x31CCM AppWdLGTW CELGTE SWERTO TUR Numerator Configuration Low Register addresses 0x57 TT Error Level Register addresses 0x3F & 0x3ETT Cycle Count Register addresses 0x3D & 0x3C TT StopWatch Register addresses 0x61 TUR Denominator Configuration Register addresses 0x59TUR Numerator Actual Registers addresses 0x5B & 0x5A Ecal QCSQgtp EgtfECS TMCDET SWSEPE TMG40/77 11.11.02 Internal can Message Handling Data Transfer Between IFx Registers and Message RAMTransmission of Messages in Event Driven can Communication StartReception of Remote Frame Acceptance Filtering of Received MessagesReception of Data Frame Storing Received Messages in Fifo BuffersReceive / Transmit Priority Configuration of the ModuleBit Time and Bit Rate Sync PropSeg PhaseSeg1 PhaseSeg21 Configuration of the Bit Timing Canclk input Nominal can Bit TimePropagation Time Segment BRPPhase Buffer Segments and Synchronisation Synchronisation on late and early Edges Filtering of Short Dominant Spikes Oscillator Tolerance Range 1.5 Configuration of the can Protocol ControllerCalculation of the Bit Timing Parameters Example for Bit Timing at high Baudrate Example for Bit Timing at low Baudrate 2 Configuration of the Message Memory2.1 Configuration of a Transmit Object for Data Frames 2.2 Configuration of a Single Receive Object for Data Frames2.3 Configuration of a Fifo Buffer Can Communication Handling of InterruptsUpdating a Transmit Object Requesting New Data for a Receive Object Changing a Transmit ObjectReading Received Messages Reading from a Fifo BufferCPU Handling of a Fifo Buffer Interrupt Driven Ttcan Configuration Ttcan TimingMessage Scheduling TUR510 125000 32.5 100/12 529/17 Trigger Memory 63/77 11.11.02 Periodic Transmit Message Message ObjectsReference Message Potential Time Masters Event Driven Transmit MessageTime Slaves Periodic Messages Ttcan Message Handling Message ReceptionMessage Transmission Event Driven MessagesTtcan Gap Control StopwatchCycle Time and Global Time Synchronisation Ttcan Interrupt and Error Handling Previous RefMarkConfiguration Example Register Remark Rdlc & TEW & CCMType & Msg & CycleCode RTO , TM , L2 , TTMode3 74/77 11.11.02 Customer Interface GenericInterface Busy = ‘1’ Busy = ‘0’ Timing of the Wait output signalCanclk Canwaitb Interrupt TimingEOF
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