Bosch Appliances TTCAN user manual BRP Extension Register addresses 0x0D & 0x0C

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TTCAN

User’s Manual

Revision 1.6

BRP Baud Rate Prescaler

0x00-0x3FThe value by which the oscillator frequency is divided for gener- ating the bit time quanta. The bit time is built up from a multiple of this quanta. Valid values for the Baud Rate Prescaler are [0 … 63]. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used.

This register is only writable if bits CCE and Init in the CAN Control Register are set. The CAN bit time may be programed in the range of [4 … 25] time quanta. The CAN time quantum may be programmed in the range of [1 … 1024] CAN_CLK periods. For details see chapter 4.2.1.

Note : With a module clock CAN_CLK of 8 MHz and BRPE = 0x00, the reset value of 0x2301 config- ures the TTCAN for a bit rate of 500 kBit/s.

3.2.5 BRP Extension Register (addresses 0x0D & 0x0C)

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BRPE Baud Rate Prescaler Extension

0x00-0x0F By programming BRPE the Baud Rate Prescaler can be extended to values up to 1023. The actual interpretation by the hardware is that one more than the value programmed by BRPE (MSBs) and BRP (LSBs) is used.

This register is only writable if bits CCE and Init in the CAN Control Register are set.

Note : The width of BRPE may be increased to more than its default width of 4 bits in particular imple- mentations of the TTCAN IP module width a high module clock frequency.

 

3.3 Message Interface Register Sets

 

 

 

 

 

 

 

 

 

 

Address

IF1 Register Set

Address

IF2 Register Set

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CAN Base+0x10

IF1 Command Request

CAN Base+0x40

IF2 Command Request

 

 

 

 

 

 

 

 

CAN Base+0x12

IF1 Command Mask

CAN Base+0x42

IF2 Command Mask

 

 

 

 

 

 

 

 

CAN Base+0x14

IF1 Mask 1

CAN Base+0x44

IF2 Mask 1

 

 

 

 

 

 

 

 

CAN Base+0x16

IF1 Mask 2

CAN Base+0x46

IF2 Mask 2

 

 

 

 

 

 

about.fm

 

CAN Base+0x18

IF1 Arbitration 1

CAN Base+0x48

IF2 Arbitration 1

 

 

 

 

 

 

CAN Base+0x1A

IF1 Arbitration 2

CAN Base+0x4A

IF2 Arbitration 2

 

 

 

 

 

 

 

 

manual

 

CAN Base+0x1C

IF1 Message Control

CAN Base+0x4C

IF2 Message Control

 

 

 

 

 

 

CAN Base+0x1E

IF1 Data A 1

CAN Base+0x4E

IF2 Data A 1

 

 

 

 

 

 

 

 

 

 

CAN Base+0x20

IF1 Data A 2

CAN Base+0x50

IF2 Data A 2

 

 

 

 

 

 

 

 

CAN Base+0x22

IF1 Data B 1

CAN Base+0x52

IF2 Data B 1

 

 

 

 

 

 

 

 

CAN Base+0x24

IF1 Data B 2

CAN Base+0x54

IF2 Data B 2

 

 

 

 

 

 

Figure 6: IF1 and IF2 Message Interface Register Sets

There are two sets of Interface Registers that control the CPU access to the Message RAM. The Interface Registers avoid (by buffering the data to be transferred) conflicts between CPU access to the Message RAM and CAN message reception and transmission. A complete Message Object (see chapter 3.3.4) or parts of the Message Object may be transferred between the Message RAM and the IFx Message Buffer registers (see chapter 3.3.3) in one

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Contents User’s Manual Robert Bosch GmbHCopyright Notice and Proprietary Information Conventions Scope References Terms and Abbreviations Functional Overview 2.2. Block Diagram Operating ModesChange Control Can Application Ttcan Configuration Ttcan Schedule InitialisationTtcan Message Handling List of FiguresChange Control Current Status Change HistoryConventions Helvetica boldTerm Meaning Functional Overview Cpuifc TtcanOperating Modes Software Initialisation Can Message TransferTest Register addresses 0x0B & 0x0A Disabled Automatic RetransmissionTest Mode Ttcan =1 Loop Back Mode Loop Back combined with Silent ModeNo Message RAM Mode Software control of Pin CantxAddress Name Reset Value Hardware Reset Description Ttcan Register SummaryCCE DAREIE SIENo Error Status Register addresses 0x03Bit Timing Register addresses 0x07 Error Counter addresses 0x05Status Interrupts BRP Extension Register addresses 0x0D & 0x0C Arb IFx Command Mask RegistersDirection = Write IFx Command Request Registers Direction = ReadControl ClrIntPndBusy Message NumberIFx Message Buffer Registers IFx Mask RegistersMessage Object in the Message Memory IFx Message Control RegistersIFx Data a and Data B Registers ID28-0 Msk28-0Xtd Dir26/77 11.11.02 Message Handler Registers Interrupt Register addresses 0x09Interrupt Pending Registers Transmission Request RegistersNew Data Registers Trigger Number 2 IF1 Data B1 and B2 Registers for Trigger Memory AccessMessage Valid 1 Register TT Operation Mode Register addresses 0x29 TypeTimeMark At CycleCount mod MPr2-0TEW EecsRdlc TT Interrupt Enable Register addresses 0x31 CCMBark AppWdLCEL GTEGTW SWERTO TUR Numerator Configuration Low Register addresses 0x57 TT Error Level Register addresses 0x3F & 0x3ETT Cycle Count Register addresses 0x3D & 0x3C TT StopWatch Register addresses 0x61 TUR Denominator Configuration Register addresses 0x59TUR Numerator Actual Registers addresses 0x5B & 0x5A QCS QgtpEcal EgtfTMC DETECS SWSEPE TMG40/77 11.11.02 Internal can Message Handling Data Transfer Between IFx Registers and Message RAMTransmission of Messages in Event Driven can Communication StartAcceptance Filtering of Received Messages Reception of Data FrameReception of Remote Frame Storing Received Messages in Fifo BuffersReceive / Transmit Priority Configuration of the ModuleSync PropSeg PhaseSeg1 PhaseSeg2 1 Configuration of the Bit TimingBit Time and Bit Rate Canclk input Nominal can Bit TimePropagation Time Segment BRPPhase Buffer Segments and Synchronisation Synchronisation on late and early Edges Filtering of Short Dominant Spikes Oscillator Tolerance Range 1.5 Configuration of the can Protocol ControllerCalculation of the Bit Timing Parameters Example for Bit Timing at high Baudrate Example for Bit Timing at low Baudrate 2 Configuration of the Message Memory2.1 Configuration of a Transmit Object for Data Frames 2.2 Configuration of a Single Receive Object for Data Frames2.3 Configuration of a Fifo Buffer Can Communication Handling of InterruptsUpdating a Transmit Object Changing a Transmit Object Reading Received MessagesRequesting New Data for a Receive Object Reading from a Fifo BufferCPU Handling of a Fifo Buffer Interrupt Driven Ttcan Configuration Ttcan TimingMessage Scheduling TUR510 125000 32.5 100/12 529/17 Trigger Memory 63/77 11.11.02 Periodic Transmit Message Message ObjectsReference Message Potential Time Masters Event Driven Transmit MessageTime Slaves Ttcan Message Handling Message Reception Message TransmissionPeriodic Messages Event Driven MessagesTtcan Gap Control StopwatchCycle Time and Global Time Synchronisation Ttcan Interrupt and Error Handling Previous RefMarkConfiguration Example Register Remark Rdlc & TEW & CCMType & Msg & CycleCode RTO , TM , L2 , TTMode3 74/77 11.11.02 Customer Interface GenericInterface Timing of the Wait output signal Canclk CanwaitbBusy = ‘1’ Busy = ‘0’ Interrupt TimingEOF
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