Bosch Appliances TTCAN user manual IFx Command Mask Registers, Direction = Write, Arb

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TTCAN

User’s Manual

Revision 1.6

manual_about.fm

single transfer. This transfer, performed in parallel on all selected parts of the Message Object, guarantees the data consistency of the CAN message. Figure 6 shows the structure of the two Interface Register sets.

The function of the two Interface Register sets is identical (except for test mode NoRAM). The second interface register set is provided to serve application programming. Two groups of software drivers may defined, each group is restricted to the use of one of the Interface Register sets. The software drivers of one group may interrupt software drivers of the other group, but not of the same group.

In a simple example, there is one Read_Message task that uses IFC1 to get received messages from the Message RAM and there is one Write_Message task that uses IFC2 to write messages to be transmitted into the Message RAM. Both tasks may interrupt each other.

Each set of Interface Registers consists of Message Buffer Registers controlled by their own Command Registers. The Command Mask Register specifies the direction of the data transfer and which parts of a Message Object will be transferred. The Command Request Register is used to select a Message Object in the Message RAM as target or source for the transfer and to start the action specified in the Command Mask Register.

3.3.1 IFx Command Mask Registers

The control bits of the IFx Command Mask Register specify the transfer direction and select which of the IFx Message Buffer Registers are source or target of the data transfer.

 

15 14 13 12 11 10 9 8

7

6

5

4

3

2

1

0

IF1 Command Mask Register

 

 

 

 

 

 

 

 

 

 

 

res

WR/RD

Mask

Arb

Control

ClrIntPnd

TxRqst/

Data A

Data B

(addresses 0x13 & 0x12)

 

NewDat

 

 

 

 

 

 

 

 

 

 

 

IF2 Command Mask Register

 

res

WR/RD

Mask

Arb

Control

ClrIntPnd

TxRqst/

Data A

Data B

(addresses 0x43 & 0x42)

 

NewDat

 

r

r r r r r r r

rw

rw

rw

rw

rw

rw

rw

rw

 

 

 

 

 

 

 

 

 

 

 

WR/RD Write / Read

one Write: Transfer data from the selected Message Buffer Registers to the Message Object addressed by the Command Request Register.

zero Read: Transfer data from the Message Object addressed by the Com- mand Request Register into the selected Message Buffer Registers.

The other bits of IFx Command Mask Register have different functions depending on the transfer direction :

3.3.1.1 Direction = Write

Mask Access Mask Bits

one transfer Identifier Mask + MDir + MXtd to Message Object. zero Mask bits unchanged.

Arb

Access Arbitration Bits

 

one

transfer Identifier + Dir + Xtd + MsgVal to Message Object.

 

zero

Arbitration bits unchanged.

Control Access Control Bits

one transfer Control Bits to Message Object. zero Control Bits unchanged.

Note : MSC2-0is read-only in time triggered operating mode.

BOSCH

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11.11.02

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Contents Robert Bosch GmbH User’s ManualCopyright Notice and Proprietary Information Functional Overview 2.2. Block Diagram Operating Modes Change ControlConventions Scope References Terms and Abbreviations Can Application Ttcan Schedule Initialisation Ttcan ConfigurationTtcan Message Handling List of FiguresChange History Change Control Current StatusConventions Helvetica boldTerm Meaning Functional Overview Ttcan CpuifcCan Message Transfer Operating Modes Software InitialisationDisabled Automatic Retransmission Test ModeTest Register addresses 0x0B & 0x0A Ttcan =1 Loop Back combined with Silent Mode Loop Back ModeSoftware control of Pin Cantx No Message RAM ModeAddress Name Reset Value Ttcan Register Summary Hardware Reset DescriptionDAR CCEEIE SIEStatus Register addresses 0x03 No ErrorError Counter addresses 0x05 Status InterruptsBit Timing Register addresses 0x07 BRP Extension Register addresses 0x0D & 0x0C IFx Command Mask Registers Direction = WriteArb Direction = Read IFx Command Request RegistersControl ClrIntPndMessage Number BusyIFx Message Buffer Registers IFx Mask RegistersIFx Message Control Registers IFx Data a and Data B RegistersMessage Object in the Message Memory Msk28-0 ID28-0Xtd Dir26/77 11.11.02 Interrupt Register addresses 0x09 Message Handler RegistersTransmission Request Registers New Data RegistersInterrupt Pending Registers 2 IF1 Data B1 and B2 Registers for Trigger Memory Access Message Valid 1 RegisterTrigger Number Type TT Operation Mode Register addresses 0x29TimeMark At CycleCount mod MPr2-0Eecs RdlcTEW CCM TT Interrupt Enable Register addresses 0x31Bark AppWdLGTE CELGTW SWERTO TT Error Level Register addresses 0x3F & 0x3E TT Cycle Count Register addresses 0x3D & 0x3CTUR Numerator Configuration Low Register addresses 0x57 TUR Denominator Configuration Register addresses 0x59 TUR Numerator Actual Registers addresses 0x5B & 0x5ATT StopWatch Register addresses 0x61 Qgtp QCSEcal EgtfDET TMCECS SWSTMG EPE40/77 11.11.02 Data Transfer Between IFx Registers and Message RAM Internal can Message HandlingStart Transmission of Messages in Event Driven can CommunicationReception of Data Frame Acceptance Filtering of Received MessagesReception of Remote Frame Storing Received Messages in Fifo BuffersConfiguration of the Module Receive / Transmit Priority1 Configuration of the Bit Timing Sync PropSeg PhaseSeg1 PhaseSeg2Bit Time and Bit Rate Canclk input Nominal can Bit TimeBRP Propagation Time SegmentPhase Buffer Segments and Synchronisation Synchronisation on late and early Edges Filtering of Short Dominant Spikes 1.5 Configuration of the can Protocol Controller Oscillator Tolerance RangeCalculation of the Bit Timing Parameters Example for Bit Timing at high Baudrate 2 Configuration of the Message Memory Example for Bit Timing at low Baudrate2.2 Configuration of a Single Receive Object for Data Frames 2.1 Configuration of a Transmit Object for Data Frames2.3 Configuration of a Fifo Buffer Handling of Interrupts Can CommunicationUpdating a Transmit Object Reading Received Messages Changing a Transmit ObjectRequesting New Data for a Receive Object Reading from a Fifo BufferCPU Handling of a Fifo Buffer Interrupt Driven Ttcan Timing Ttcan ConfigurationTUR 510 125000 32.5 100/12 529/17Message Scheduling Trigger Memory 63/77 11.11.02 Message Objects Reference MessagePeriodic Transmit Message Event Driven Transmit Message Time SlavesPotential Time Masters Message Transmission Ttcan Message Handling Message ReceptionPeriodic Messages Event Driven MessagesStopwatch Ttcan Gap ControlCycle Time and Global Time Synchronisation Previous RefMark Ttcan Interrupt and Error HandlingConfiguration Example Rdlc & TEW & CCM Register RemarkType & Msg & CycleCode RTO , TM , L2 , TTMode3 74/77 11.11.02 Generic InterfaceCustomer Interface Canclk Canwaitb Timing of the Wait output signalBusy = ‘1’ Busy = ‘0’ Interrupt TimingEOF
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