Bosch Appliances TTCAN user manual Ttcan Register Summary, Hardware Reset Description

Page 16

 

TTCAN

User’s Manual

Revision 1.6

 

 

 

 

 

 

 

 

 

Address

Name

Reset Value

Note

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CAN Base+0x48

IF2 Arbitration 1

0x0000

CAN appl. IF2 Register Set

 

 

 

 

 

 

 

 

 

 

CAN Base+0x4A

IF2 Arbitration 2

0x0000

 

 

 

 

 

 

 

 

 

 

 

CAN Base+0x4C

IF2 Message Control

0x0000

 

 

 

 

 

 

 

 

 

 

 

CAN Base+0x4E

IF2 Data A 1

0x0000

 

 

 

 

 

 

 

 

 

 

 

CAN Base+0x50

IF2 Data A 2

0x0000

 

 

 

 

 

 

 

 

 

 

 

CAN Base+0x52

IF2 Data B 1

0x0000

 

 

 

 

 

 

 

 

 

 

 

CAN Base+0x54

IF2 Data B 2

0x0000

 

 

 

 

 

 

 

 

 

 

 

CAN Base+0x56

TUR-NumeratorCfg

0x0000

TTCAN config register

 

 

 

 

 

 

 

 

 

 

CAN Base+0x58

TUR-DenominatorCfg

0x1000

TTCAN config register

 

 

 

 

 

 

 

 

 

 

CAN Base+0x5A

TUR-NumeratorActL

0x0000

TTCAN status register

 

 

 

 

 

 

 

 

 

 

CAN Base+0x5C

TUR-NumeratorActH

0x0001

TTCAN status register

 

 

 

 

 

 

 

 

 

 

CAN Base+0x5E

— reserved

— 2)

 

 

 

 

CAN Base+0x60

Stop_Watch

0x0000

TTCAN status register

 

 

 

 

 

 

 

 

 

 

CAN Base+0x62

— reserved

— 2)

 

 

 

 

CAN Base+0x64

Global Time Preset

0x0000

TTCAN appl. register

 

 

 

 

 

 

 

 

 

 

CAN Base+0x66

Clock Control

0x1000

TTCAN appl. register

 

 

 

 

 

 

 

 

 

 

CAN Base+0x68

Sync_Mark

0x0000

TTCAN status register

 

 

 

 

 

 

 

 

 

 

CAN Base+0x6A

— reserved

— 2)

 

 

 

 

CAN Base+0x6C

Time Mark

0x0000

TTCAN appl. register

 

 

 

 

 

 

 

 

 

 

CAN Base+0x6E

Gap Control

0x0000

TTCAN appl. register

 

 

 

 

 

 

 

 

 

 

CAN Base+0x70-0x7E

— reserved

— 2)

 

 

 

 

CAN Base+0x80

Transmission Request 1

0x0000

CAN status register

 

 

 

 

 

 

 

 

 

 

CAN Base+0x82

Transmission Request 2

0x0000

CAN status register

 

 

 

 

 

 

 

 

 

 

CAN Base+0x84-0x8E

— reserved

— 2)

 

 

 

 

CAN Base+0x90

New Data 1

0x0000

CAN status register

 

 

 

 

 

 

 

 

 

 

CAN Base+0x92

New Data 2

0x0000

CAN status register

 

 

 

 

 

 

 

 

 

 

CAN Base+0x94-0x9E

— reserved

— 2)

 

 

 

 

CAN Base+0xA0

Interrupt Pending 1

0x0000

CAN status register

 

 

 

 

 

 

 

 

 

 

CAN Base+0xA2

Interrupt Pending 2

0x0000

CAN status register

 

 

 

 

 

 

 

 

 

 

CAN Base+0xA4-0xAE

— reserved

— 2)

 

 

 

 

CAN Base+0xB0

Message Valid 1

0x0000

CAN status register

 

 

 

 

 

 

 

 

 

 

CAN Base+0xB2

Message Valid 2

0x0000

CAN status register

 

 

 

 

 

 

 

 

about.fm

 

CAN Base+0xB4-0xBE

— reserved

— 2)

 

 

 

 

 

 

 

 

1) r signifies the actual value of the CAN_RX pin.

 

 

 

_

 

 

 

 

 

 

manual

 

2) Reserved bits are read as ’0’ except for IFx Mask 2 Register where they are read as ’1’

 

 

 

 

Figure 5: TTCAN Register Summary

3.1 Hardware Reset Description

After hardware reset, the registers of the TTCAN hold the values described in figure 5.

Additionally the Bus_Off state is reset and the output CAN_TX is set to recessive (HIGH). The value 0x0001 (Init = ‘1’) in the CAN Control Register enables the software initialisation. The TTCAN does not influence the CAN bus until the CPU resets Init to ‘0’.

The data in the Message RAM is (apart from the MsgVal, NewDat, TxRqst, and IntPnd bits) not affected by a hardware reset. After power-on, the contents of the Message RAM is undefined.

BOSCH

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11.11.02

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Contents User’s Manual Robert Bosch GmbHCopyright Notice and Proprietary Information Change Control Functional Overview 2.2. Block Diagram Operating ModesConventions Scope References Terms and Abbreviations Can Application Ttcan Configuration Ttcan Schedule InitialisationTtcan Message Handling List of FiguresChange Control Current Status Change HistoryConventions Helvetica boldTerm Meaning Functional Overview Cpuifc TtcanOperating Modes Software Initialisation Can Message TransferTest Mode Disabled Automatic RetransmissionTest Register addresses 0x0B & 0x0A Ttcan =1 Loop Back Mode Loop Back combined with Silent ModeNo Message RAM Mode Software control of Pin CantxAddress Name Reset Value Hardware Reset Description Ttcan Register SummaryCCE DAREIE SIENo Error Status Register addresses 0x03Status Interrupts Error Counter addresses 0x05Bit Timing Register addresses 0x07 BRP Extension Register addresses 0x0D & 0x0C Direction = Write IFx Command Mask RegistersArb IFx Command Request Registers Direction = ReadControl ClrIntPndBusy Message NumberIFx Message Buffer Registers IFx Mask RegistersIFx Data a and Data B Registers IFx Message Control RegistersMessage Object in the Message Memory ID28-0 Msk28-0Xtd Dir26/77 11.11.02 Message Handler Registers Interrupt Register addresses 0x09New Data Registers Transmission Request RegistersInterrupt Pending Registers Message Valid 1 Register 2 IF1 Data B1 and B2 Registers for Trigger Memory AccessTrigger Number TT Operation Mode Register addresses 0x29 TypeTimeMark At CycleCount mod MPr2-0Rdlc EecsTEW TT Interrupt Enable Register addresses 0x31 CCMBark AppWdLCEL GTEGTW SWERTO TT Cycle Count Register addresses 0x3D & 0x3C TT Error Level Register addresses 0x3F & 0x3ETUR Numerator Configuration Low Register addresses 0x57 TUR Numerator Actual Registers addresses 0x5B & 0x5A TUR Denominator Configuration Register addresses 0x59TT StopWatch Register addresses 0x61 QCS QgtpEcal EgtfTMC DETECS SWSEPE TMG40/77 11.11.02 Internal can Message Handling Data Transfer Between IFx Registers and Message RAMTransmission of Messages in Event Driven can Communication StartAcceptance Filtering of Received Messages Reception of Data FrameReception of Remote Frame Storing Received Messages in Fifo BuffersReceive / Transmit Priority Configuration of the ModuleSync PropSeg PhaseSeg1 PhaseSeg2 1 Configuration of the Bit TimingBit Time and Bit Rate Canclk input Nominal can Bit TimePropagation Time Segment BRPPhase Buffer Segments and Synchronisation Synchronisation on late and early Edges Filtering of Short Dominant Spikes Oscillator Tolerance Range 1.5 Configuration of the can Protocol ControllerCalculation of the Bit Timing Parameters Example for Bit Timing at high Baudrate Example for Bit Timing at low Baudrate 2 Configuration of the Message Memory2.1 Configuration of a Transmit Object for Data Frames 2.2 Configuration of a Single Receive Object for Data Frames2.3 Configuration of a Fifo Buffer Can Communication Handling of InterruptsUpdating a Transmit Object Changing a Transmit Object Reading Received MessagesRequesting New Data for a Receive Object Reading from a Fifo BufferCPU Handling of a Fifo Buffer Interrupt Driven Ttcan Configuration Ttcan Timing510 125000 32.5 100/12 529/17 TURMessage Scheduling Trigger Memory 63/77 11.11.02 Reference Message Message ObjectsPeriodic Transmit Message Time Slaves Event Driven Transmit MessagePotential Time Masters Ttcan Message Handling Message Reception Message TransmissionPeriodic Messages Event Driven MessagesTtcan Gap Control StopwatchCycle Time and Global Time Synchronisation Ttcan Interrupt and Error Handling Previous RefMarkConfiguration Example Register Remark Rdlc & TEW & CCMType & Msg & CycleCode RTO , TM , L2 , TTMode3 74/77 11.11.02 Interface GenericCustomer Interface Timing of the Wait output signal Canclk CanwaitbBusy = ‘1’ Busy = ‘0’ Interrupt TimingEOF
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