Bosch Appliances TTCAN user manual Cel, Gte, Gtw, Swe, Tmi, Csm, Ssm, Sbc

Page 33

TTCAN

User’s Manual

Revision 1.6

manual_about.fm

Any number of bits may be written to ‘0’ (cleared) at the same time. Bits that are written to ‘1’ remain unchanged.

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CfE

ApW

WTr

IWT

CEL

TxO

TxU

GTE

Dis

GTW

SWE

TMI

SoG

CSM

SSM

SBC

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CfE Conﬁg Error

Set when an error is found in the Trigger List.

ApW Application Watchdog

Set when the application watchdog was not served in time.

WTr Watch Trigger

Set when a Watch Trigger became active (missing Reference Message).

IWT Initialisation Watch Trigger

Set when an Initialisation Watch Trigger became active (no system start-up).

Note : The initialisation is restarted by resetting IWT.

CEL	Change of Error Level
	Set when the Error Level changed.
TxO	Tx_Count Overﬂow
	Set when the FSE sees more than Expected_Tx_Trigger in one Matrix Cycle.
TxU	Tx_Count Underﬂow
	Set when the FSE sees less than Expected_Tx_Trigger in one Matrix Cycle.
GTE	Global Time Error
	Set when Synchronisation Deviation SD exceeds speciﬁed limit SDL (level2 only).
Dis	Global Time Discontinuity
	Set on discontinuity of the Global Time (Disc_Bit in the Reference Message).
GTW	Global Time Wrap
	Set when a Global Time wrap occurred (from 0xFFFF to 0x0000).
SWE	Stop Watch Event
	Set when a rising edge is detected at the STOP_WATCH_TRIGGER pin.
TMI	Time Mark Interrupt
	Set when the selected time equals value in Time Mark register.
SoG	Start of Gap
	Set when a Gap is detected (Next_is_Gap bit in the Reference Message).
CSM	Change of Synchronisation Mode
	Set when the master to slave relation or the schedule synchronisation changed.
SSM	Start of System Matrix Cycle
	Set when a new System Matrix Cycle has started.
SBC	Start of Basic Cycle
	Set when a new Basic Cycle has started.

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Contents Robert Bosch GmbH User’s ManualCopyright Notice and Proprietary Information Functional Overview 2.2. Block Diagram Operating Modes Change ControlConventions Scope References Terms and Abbreviations Can Application Ttcan Schedule Initialisation Ttcan ConfigurationTtcan Message Handling List of FiguresChange History Change Control Current StatusConventions Helvetica boldTerm Meaning Functional Overview Ttcan CpuifcCan Message Transfer Operating Modes Software InitialisationDisabled Automatic Retransmission Test ModeTest Register addresses 0x0B & 0x0A Ttcan =1 Loop Back combined with Silent Mode Loop Back ModeSoftware control of Pin Cantx No Message RAM ModeAddress Name Reset Value Ttcan Register Summary Hardware Reset DescriptionDAR CCEEIE SIEStatus Register addresses 0x03 No ErrorError Counter addresses 0x05 Status InterruptsBit Timing Register addresses 0x07 BRP Extension Register addresses 0x0D & 0x0C IFx Command Mask Registers Direction = WriteArb Direction = Read IFx Command Request RegistersControl ClrIntPndMessage Number BusyIFx Message Buffer Registers IFx Mask RegistersIFx Message Control Registers IFx Data a and Data B RegistersMessage Object in the Message Memory Msk28-0 ID28-0Xtd Dir26/77 11.11.02 Interrupt Register addresses 0x09 Message Handler RegistersTransmission Request Registers New Data RegistersInterrupt Pending Registers 2 IF1 Data B1 and B2 Registers for Trigger Memory Access Message Valid 1 RegisterTrigger Number Type TT Operation Mode Register addresses 0x29TimeMark At CycleCount mod MPr2-0Eecs RdlcTEW CCM TT Interrupt Enable Register addresses 0x31Bark AppWdLGTE CELGTW SWERTO TT Error Level Register addresses 0x3F & 0x3E TT Cycle Count Register addresses 0x3D & 0x3CTUR Numerator Conﬁguration Low Register addresses 0x57 TUR Denominator Conﬁguration Register addresses 0x59 TUR Numerator Actual Registers addresses 0x5B & 0x5ATT StopWatch Register addresses 0x61 Qgtp QCSEcal EgtfDET TMCECS SWSTMG EPE40/77 11.11.02 Data Transfer Between IFx Registers and Message RAM Internal can Message HandlingStart Transmission of Messages in Event Driven can CommunicationReception of Data Frame Acceptance Filtering of Received MessagesReception of Remote Frame Storing Received Messages in Fifo BuffersConﬁguration of the Module Receive / Transmit Priority1 Conﬁguration of the Bit Timing Sync PropSeg PhaseSeg1 PhaseSeg2Bit Time and Bit Rate Canclk input Nominal can Bit TimeBRP Propagation Time SegmentPhase Buffer Segments and Synchronisation Synchronisation on late and early Edges Filtering of Short Dominant Spikes 1.5 Conﬁguration of the can Protocol Controller Oscillator Tolerance RangeCalculation of the Bit Timing Parameters Example for Bit Timing at high Baudrate 2 Conﬁguration of the Message Memory Example for Bit Timing at low Baudrate2.2 Conﬁguration of a Single Receive Object for Data Frames 2.1 Conﬁguration of a Transmit Object for Data Frames2.3 Conﬁguration of a Fifo Buffer Handling of Interrupts Can CommunicationUpdating a Transmit Object Reading Received Messages Changing a Transmit ObjectRequesting New Data for a Receive Object Reading from a Fifo BufferCPU Handling of a Fifo Buffer Interrupt Driven Ttcan Timing Ttcan ConﬁgurationTUR 510 125000 32.5 100/12 529/17Message Scheduling Trigger Memory 63/77 11.11.02 Message Objects Reference MessagePeriodic Transmit Message Event Driven Transmit Message Time SlavesPotential Time Masters Message Transmission Ttcan Message Handling Message ReceptionPeriodic Messages Event Driven MessagesStopwatch Ttcan Gap ControlCycle Time and Global Time Synchronisation Previous RefMark Ttcan Interrupt and Error HandlingConﬁguration Example Rdlc & TEW & CCM Register RemarkType & Msg & CycleCode RTO , TM , L2 , TTMode3 74/77 11.11.02 Generic InterfaceCustomer Interface Canclk Canwaitb Timing of the Wait output signalBusy = ‘1’ Busy = ‘0’ Interrupt TimingEOF