Bosch Appliances TTCAN user manual ID28-0, Msk28-0, Xtd, Dir

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TTCAN

User’s Manual

Revision 1.6

manual_about.fm

ID28-0

Message Identifier

 

ID28 - ID0

29-bit Identifier (“Extended Frame”).

 

ID28 - ID18

11-bit Identifier (“Standard Frame”).

Msk28-0

Identifier Mask

 

 

one

The corresponding identifier bit is used for acceptance filtering.

 

zero

The corresponding bit in the identifier of the message object cannot inhibit

 

 

the match in the acceptance filtering.

Xtd

Extended Identifier

 

one

The 29-bit (“extended”) Identifier will be used for this Message Object.

 

zero

The 11-bit (“standard”) Identifier will be used for this Message Object.

MXtd Mask Extended Identifier

one The extended identifier bit (IDE) is used for acceptance filtering.

zero The extended identifier bit (IDE) has no effect on the acceptance filtering

Note : When 11-bit (“standard”) Identifiers are used for a Message Object, the identifiers of received Data Frames are written into bits ID28 to ID18. For acceptance filtering, only these bits together with mask bits Msk28 to Msk18 are considered.

Dir

Message Direction

 

one

Direction = transmit: On TxRqst, the respective Message Object is trans-

 

 

mitted as a Data Frame. On reception of a Remote Frame with matching

 

 

identifier, the TxRqst bit of this Message Object is set (if RmtEn = one).

 

zero

Direction = receive: On TxRqst, a Remote Frame with the identifier of this

 

 

Message Object is transmitted. On reception of a Data Frame with match-

 

 

ing identifier, that message is stored in this Message Object.

MDir Mask Message Direction

one The message direction bit (Dir) is used for acceptance filtering.

zero The message direction bit (Dir) has no effect on the acceptance filtering. The Arbitration Registers ID28-0, Xtd, and Dir are used to define the identifier and type of outgoing messages and are used (together with the mask registers Msk28-0, MXtd, and MDir) for acceptance filtering of incoming messages. A received message is stored into the valid Message Object with matching identifier and Direction=receive (Data Frame) or Direction=transmit (Remote Frame). Extended frames can be stored only in Message Objects with Xtd = one, standard frames in Message Objects with Xtd = zero. If a received message (Data Frame or Remote Frame) matches with more than one valid Message Object, it is stored into that with the lowest message number. For details see chapter 4.1.3 Acceptance Filtering of Received Messages.

EoB End of Block

one Single Message Object or last Message Object of a FIFO Buffer Block. zero Message Object belongs to a FIFO Buffer Block and is not the last Mes-

sage Object of that FIFO Buffer Block.

Note : This bit is used to concatenate two ore more Message Objects (up to 32) to build a FIFO Buffer.

For single Message Objects (not belonging to a FIFO Buffer) this bit must always be set to one. For details on the concatenation of Message Objects see chapter 4.2.2.3.

MSC2-0Message Status Count

0-7The actual value of the Message Status Count, read-only in active mode.

Note : The Message Status Count is status information that is generated for periodic Message Objects in Time Triggered Communication (ISO11898-4). It has no function in Event Driven CAN Com- munication (ISO11898-1) and for arbitrating Message Objects in TTCAN.

BOSCH

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11.11.02

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Contents Robert Bosch GmbH User’s ManualCopyright Notice and Proprietary Information Change Control Functional Overview 2.2. Block Diagram Operating ModesConventions Scope References Terms and Abbreviations Can Application Ttcan Schedule Initialisation Ttcan ConfigurationTtcan Message Handling List of FiguresChange History Change Control Current StatusConventions Helvetica boldTerm Meaning Functional Overview Ttcan CpuifcCan Message Transfer Operating Modes Software InitialisationTest Mode Disabled Automatic RetransmissionTest Register addresses 0x0B & 0x0A Ttcan =1 Loop Back combined with Silent Mode Loop Back ModeSoftware control of Pin Cantx No Message RAM ModeAddress Name Reset Value Ttcan Register Summary Hardware Reset DescriptionDAR CCEEIE SIEStatus Register addresses 0x03 No ErrorStatus Interrupts Error Counter addresses 0x05Bit Timing Register addresses 0x07 BRP Extension Register addresses 0x0D & 0x0C Direction = Write IFx Command Mask RegistersArb Direction = Read IFx Command Request Registers Control ClrIntPndMessage Number BusyIFx Message Buffer Registers IFx Mask RegistersIFx Data a and Data B Registers IFx Message Control RegistersMessage Object in the Message Memory Msk28-0 ID28-0Xtd Dir26/77 11.11.02 Interrupt Register addresses 0x09 Message Handler RegistersNew Data Registers Transmission Request RegistersInterrupt Pending Registers Message Valid 1 Register 2 IF1 Data B1 and B2 Registers for Trigger Memory AccessTrigger Number Type TT Operation Mode Register addresses 0x29TimeMark At CycleCount mod MPr2-0Rdlc EecsTEW CCM TT Interrupt Enable Register addresses 0x31Bark AppWdLGTE CELGTW SWERTO TT Cycle Count Register addresses 0x3D & 0x3C TT Error Level Register addresses 0x3F & 0x3ETUR Numerator Configuration Low Register addresses 0x57 TUR Numerator Actual Registers addresses 0x5B & 0x5A TUR Denominator Configuration Register addresses 0x59TT StopWatch Register addresses 0x61 Qgtp QCSEcal EgtfDET TMCECS SWSTMG EPE40/77 11.11.02 Data Transfer Between IFx Registers and Message RAM Internal can Message HandlingStart Transmission of Messages in Event Driven can CommunicationReception of Data Frame Acceptance Filtering of Received MessagesReception of Remote Frame Storing Received Messages in Fifo BuffersConfiguration of the Module Receive / Transmit Priority1 Configuration of the Bit Timing Sync PropSeg PhaseSeg1 PhaseSeg2Bit Time and Bit Rate Canclk input Nominal can Bit TimeBRP Propagation Time SegmentPhase Buffer Segments and Synchronisation Synchronisation on late and early Edges Filtering of Short Dominant Spikes 1.5 Configuration of the can Protocol Controller Oscillator Tolerance RangeCalculation of the Bit Timing Parameters Example for Bit Timing at high Baudrate 2 Configuration of the Message Memory Example for Bit Timing at low Baudrate2.2 Configuration of a Single Receive Object for Data Frames 2.1 Configuration of a Transmit Object for Data Frames2.3 Configuration of a Fifo Buffer Handling of Interrupts Can CommunicationUpdating a Transmit Object Reading Received Messages Changing a Transmit ObjectRequesting New Data for a Receive Object Reading from a Fifo BufferCPU Handling of a Fifo Buffer Interrupt Driven Ttcan Timing Ttcan Configuration510 125000 32.5 100/12 529/17 TURMessage Scheduling Trigger Memory 63/77 11.11.02 Reference Message Message ObjectsPeriodic Transmit Message Time Slaves Event Driven Transmit MessagePotential Time Masters Message Transmission Ttcan Message Handling Message ReceptionPeriodic Messages Event Driven MessagesStopwatch Ttcan Gap ControlCycle Time and Global Time Synchronisation Previous RefMark Ttcan Interrupt and Error HandlingConfiguration Example Rdlc & TEW & CCM Register RemarkType & Msg & CycleCode RTO , TM , L2 , TTMode3 74/77 11.11.02 Interface GenericCustomer Interface Canclk Canwaitb Timing of the Wait output signalBusy = ‘1’ Busy = ‘0’ Interrupt TimingEOF
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