Bosch Appliances TTCAN user manual Changing a Transmit Object, Reading Received Messages

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TTCAN

User’s Manual

Revision 1.6

manual_about.fm

4.3.3 Changing a Transmit Object

In an application for that the number of Message Objects in the TTCAN module is not sufficient, the Transmit Objects may be managed dynamically. The CPU writes the whole message (Arbitration, Control, and Data) into the Interface Register. The Command Mask Register is set to 0x00B7 for the transfer of the contents into the designated Message Object. Neither MsgVal nor TxRqst have to be reset before this operation.

If a previously requested transmission of that Message Object is not completed but already in progress, it will be continued; it will however not be repeated if it is disturbed.

4.3.4 Reading Received Messages

The CPU may read a received message any time via the IFx Interface Registers, the data consistency is guaranteed by the Message Handler state machine.

Typically the CPU will write first 0x007F to the Command Mask Register and then the number of the Message Object to the Command Request Register. That combination will transfer the whole received message from the Message RAM into the Message Buffer Register. Additionally, the bits NewDat and IntPnd are cleared in the Message RAM (not in the Message Buffer). The values of these bits in the Message Control Register always reflect the status before resetting the bits.

If the Message Object uses masks for acceptance filtering, the arbitration bits show which of the different matching messages has been received.

The actual value of NewDat shows whether a new message has been received since last time this Message Object was read. The actual value of MsgLst shows whether more than one message has been received since last time this Message Object was read. MsgLst will not be automatically reset.

4.3.5 Requesting New Data for a Receive Object

By means of a Remote Frame, the CPU may request another CAN node to provide new data for a receive object. Setting the TxRqst bit of a receive object will cause the transmission of a Remote Frame with the receive object’s identifier. This Remote Frame triggers the other CAN node to start the transmission of the matching Data Frame. If the matching Data Frame is received before the Remote Frame could be transmitted, the TxRqst bit is automatically reset.

Setting the TxRqst bit without changing the contents of a Message Object requires the value 0x0084 in the Command Mask Register.

4.3.6 Reading from a FIFO Buffer

Several messages may be accumulated in a set of Message Objects which are concatenated to form a FIFO Buffer before the application program is required (in order to avoid the loss of data) to empty the buffer. A FIFO Buffer of length N will store the first (N-1) and the last received message since last time it was cleared.

A FIFO Buffer is cleared by reading and resetting the NewDat bits of all its Message Objects, starting at the FIFO Object with the lowest message number. This should be done in a subroutine following the example shown in figure 17.

Reading from a FIFO Buffer Message Object and resetting its NewDat bit is handled the same way as reading from a single Message Object.

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Contents User’s Manual Robert Bosch GmbHCopyright Notice and Proprietary Information Change Control Functional Overview 2.2. Block Diagram Operating ModesConventions Scope References Terms and Abbreviations Can Application Ttcan Message Handling Ttcan ConfigurationTtcan Schedule Initialisation List of FiguresConventions Change Control Current StatusChange History Helvetica boldTerm Meaning Functional Overview Cpuifc TtcanOperating Modes Software Initialisation Can Message TransferTest Mode Disabled Automatic RetransmissionTest Register addresses 0x0B & 0x0A Ttcan =1 Loop Back Mode Loop Back combined with Silent ModeNo Message RAM Mode Software control of Pin CantxAddress Name Reset Value Hardware Reset Description Ttcan Register SummaryEIE CCEDAR SIENo Error Status Register addresses 0x03Status Interrupts Error Counter addresses 0x05Bit Timing Register addresses 0x07 BRP Extension Register addresses 0x0D & 0x0C Direction = Write IFx Command Mask RegistersArb Control IFx Command Request RegistersDirection = Read ClrIntPndIFx Message Buffer Registers BusyMessage Number IFx Mask RegistersIFx Data a and Data B Registers IFx Message Control RegistersMessage Object in the Message Memory Xtd ID28-0Msk28-0 Dir26/77 11.11.02 Message Handler Registers Interrupt Register addresses 0x09New Data Registers Transmission Request RegistersInterrupt Pending Registers Message Valid 1 Register 2 IF1 Data B1 and B2 Registers for Trigger Memory AccessTrigger Number TimeMark At CycleCount mod TT Operation Mode Register addresses 0x29Type MPr2-0Rdlc EecsTEW Bark TT Interrupt Enable Register addresses 0x31CCM AppWdLGTW CELGTE SWERTO TT Cycle Count Register addresses 0x3D & 0x3C TT Error Level Register addresses 0x3F & 0x3ETUR Numerator Configuration Low Register addresses 0x57 TUR Numerator Actual Registers addresses 0x5B & 0x5A TUR Denominator Configuration Register addresses 0x59TT StopWatch Register addresses 0x61 Ecal QCSQgtp EgtfECS TMCDET SWSEPE TMG40/77 11.11.02 Internal can Message Handling Data Transfer Between IFx Registers and Message RAMTransmission of Messages in Event Driven can Communication StartReception of Remote Frame Acceptance Filtering of Received MessagesReception of Data Frame Storing Received Messages in Fifo BuffersReceive / Transmit Priority Configuration of the ModuleBit Time and Bit Rate Sync PropSeg PhaseSeg1 PhaseSeg21 Configuration of the Bit Timing Canclk input Nominal can Bit TimePropagation Time Segment BRPPhase Buffer Segments and Synchronisation Synchronisation on late and early Edges Filtering of Short Dominant Spikes Oscillator Tolerance Range 1.5 Configuration of the can Protocol ControllerCalculation of the Bit Timing Parameters Example for Bit Timing at high Baudrate Example for Bit Timing at low Baudrate 2 Configuration of the Message Memory2.1 Configuration of a Transmit Object for Data Frames 2.2 Configuration of a Single Receive Object for Data Frames2.3 Configuration of a Fifo Buffer Can Communication Handling of InterruptsUpdating a Transmit Object Requesting New Data for a Receive Object Changing a Transmit ObjectReading Received Messages Reading from a Fifo BufferCPU Handling of a Fifo Buffer Interrupt Driven Ttcan Configuration Ttcan Timing510 125000 32.5 100/12 529/17 TURMessage Scheduling Trigger Memory 63/77 11.11.02 Reference Message Message ObjectsPeriodic Transmit Message Time Slaves Event Driven Transmit MessagePotential Time Masters Periodic Messages Ttcan Message Handling Message ReceptionMessage Transmission Event Driven MessagesTtcan Gap Control StopwatchCycle Time and Global Time Synchronisation Ttcan Interrupt and Error Handling Previous RefMarkConfiguration Example Register Remark Rdlc & TEW & CCMType & Msg & CycleCode RTO , TM , L2 , TTMode3 74/77 11.11.02 Interface GenericCustomer Interface Busy = ‘1’ Busy = ‘0’ Timing of the Wait output signalCanclk Canwaitb Interrupt TimingEOF
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