Bosch Appliances TTCAN user manual Ttcan Interrupt and Error Handling, Previous RefMark

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TTCAN

User’s Manual

Revision 1.6

Start of	actual Ref Mark	Sync Mark
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Reference Message

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Figure 20: TTCAN Level 2 Drift Compensation

Figure 20 describes how in TTCAN Level 2 each time receiving node compensates the drift between its own local clock and the Time Master’s clock by comparing the length of a Basic Cycle in Local Time and in Global Time. If there is a difference between the two values and the Disc_Bit in the Reference Message is not set, a new value for NumAct is calculated. If the Synchronisation Deviation SD = NumCfg-NumAct≤SDL(Synchronisation Deviation Limit), the new value for NumAct takes effect. Else the automatic drift compensation is suspended.

In TTCAN Level 2, QCS in the Clock Control register shows whether the automatic drift compensation is active or suspended. In TTCAN Level 1, QCS is always ‘1’.

The current Time Master may synchronise its local clock speed and the Global Time phase to an external clock source. Both actions require that EECS in the Operating Mode Register is set.

The Stopwatch (see chapter 3.5.18 and chapter 5.5) may be used to measure the difference in clock speed between the local clock and the external clock. The local clock speed is adjusted by ﬁrst writing the newly calculated NumCfg value (DenomCfg cannot be updated) into the TUR Numerator Conﬁguration register. The new value takes effect by writing ‘1’ to the ECS bit of the Clock Control register.

The Global Time phase is adjusted by ﬁrst writing the phase offset into the Global Time Preset register. The new value takes effect by writing ‘1’ to the SGT bit of the Clock Control register. The ﬁrst Reference Message transmitted after the Global Time phase adjustment will contain the Disc_Bit=‘1’.

QGTP in the Clock Control register shows whether the node’s Global Time is in phase with the Time Master’s Global Time. QGTP is permanently ‘0’ in TTCAN Level 1 and when the Synchronisation Deviation Limit is exceeded in TTCAN Level 2 (QCS=‘0’). It is temporarily ‘0’ while the Global Time is low-pass ﬁltered to avoid an un-reasonableness in the value provided to the application. There is no low-pass ﬁltering when the last Reference Message’s contained a Disc_Bit=‘1’ or when QCS=‘0’.

5.7 TTCAN Interrupt and Error Handling

The TTCAN module provides the same interrupts as the C_CAN module (see chapter 4.3.1) as well as the additional TT Interrupt Vector.

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Contents Robert Bosch GmbH User’s ManualCopyright Notice and Proprietary Information Functional Overview 2.2. Block Diagram Operating Modes Change ControlConventions Scope References Terms and Abbreviations Can Application Ttcan Schedule Initialisation Ttcan ConfigurationTtcan Message Handling List of FiguresChange History Change Control Current StatusConventions Helvetica boldTerm Meaning Functional Overview Ttcan CpuifcCan Message Transfer Operating Modes Software InitialisationDisabled Automatic Retransmission Test ModeTest Register addresses 0x0B & 0x0A Ttcan =1 Loop Back combined with Silent Mode Loop Back ModeSoftware control of Pin Cantx No Message RAM ModeAddress Name Reset Value Ttcan Register Summary Hardware Reset DescriptionDAR CCEEIE SIEStatus Register addresses 0x03 No ErrorError Counter addresses 0x05 Status InterruptsBit Timing Register addresses 0x07 BRP Extension Register addresses 0x0D & 0x0C IFx Command Mask Registers Direction = WriteArb Direction = Read IFx Command Request RegistersControl ClrIntPndMessage Number BusyIFx Message Buffer Registers IFx Mask RegistersIFx Message Control Registers IFx Data a and Data B RegistersMessage Object in the Message Memory Msk28-0 ID28-0Xtd Dir26/77 11.11.02 Interrupt Register addresses 0x09 Message Handler RegistersTransmission Request Registers New Data RegistersInterrupt Pending Registers 2 IF1 Data B1 and B2 Registers for Trigger Memory Access Message Valid 1 RegisterTrigger Number Type TT Operation Mode Register addresses 0x29TimeMark At CycleCount mod MPr2-0Eecs RdlcTEW CCM TT Interrupt Enable Register addresses 0x31Bark AppWdLGTE CELGTW SWERTO TT Error Level Register addresses 0x3F & 0x3E TT Cycle Count Register addresses 0x3D & 0x3CTUR Numerator Conﬁguration Low Register addresses 0x57 TUR Denominator Conﬁguration Register addresses 0x59 TUR Numerator Actual Registers addresses 0x5B & 0x5ATT StopWatch Register addresses 0x61 Qgtp QCSEcal EgtfDET TMCECS SWSTMG EPE40/77 11.11.02 Data Transfer Between IFx Registers and Message RAM Internal can Message HandlingStart Transmission of Messages in Event Driven can CommunicationReception of Data Frame Acceptance Filtering of Received MessagesReception of Remote Frame Storing Received Messages in Fifo BuffersConﬁguration of the Module Receive / Transmit Priority1 Conﬁguration of the Bit Timing Sync PropSeg PhaseSeg1 PhaseSeg2Bit Time and Bit Rate Canclk input Nominal can Bit TimeBRP Propagation Time SegmentPhase Buffer Segments and Synchronisation Synchronisation on late and early Edges Filtering of Short Dominant Spikes 1.5 Conﬁguration of the can Protocol Controller Oscillator Tolerance RangeCalculation of the Bit Timing Parameters Example for Bit Timing at high Baudrate 2 Conﬁguration of the Message Memory Example for Bit Timing at low Baudrate2.2 Conﬁguration of a Single Receive Object for Data Frames 2.1 Conﬁguration of a Transmit Object for Data Frames2.3 Conﬁguration of a Fifo Buffer Handling of Interrupts Can CommunicationUpdating a Transmit Object Reading Received Messages Changing a Transmit ObjectRequesting New Data for a Receive Object Reading from a Fifo BufferCPU Handling of a Fifo Buffer Interrupt Driven Ttcan Timing Ttcan ConﬁgurationTUR 510 125000 32.5 100/12 529/17Message Scheduling Trigger Memory 63/77 11.11.02 Message Objects Reference MessagePeriodic Transmit Message Event Driven Transmit Message Time SlavesPotential Time Masters Message Transmission Ttcan Message Handling Message Reception Periodic Messages Event Driven MessagesStopwatch Ttcan Gap ControlCycle Time and Global Time Synchronisation Previous RefMark Ttcan Interrupt and Error HandlingConﬁguration Example Rdlc & TEW & CCM Register RemarkType & Msg & CycleCode RTO , TM , L2 , TTMode3 74/77 11.11.02 Generic InterfaceCustomer Interface Canclk Canwaitb Timing of the Wait output signalBusy = ‘1’ Busy = ‘0’ Interrupt TimingEOF