Bosch Appliances TTCAN Event Driven Transmit Message, Time Slaves, Potential Time Masters

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TTCAN

User’s Manual

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TxRqst and RmtEn may never be set for a periodic transmit message. To enable the transmission of a periodic message inside an Exclusive Time Window, TxRqst has to be set to ‘0’ and NewDat has to be set to ‘1’. The message will be transmitted each time its Tx_Trigger(s) become(s) active, neither TxRqst nor NewDat will be changed. MSC will be updated according to the success of the transmissions.

The application program has to ensure that all data of the periodic transmit messages are valid before the time triggered communication is started.

5.1.4.3 Event Driven Transmit Message

The configuration of an event driven transmit message for the transmission inside an Arbitrating Time Window is the same as for “Event driven Communication”. The combination of TxRqst=‘0’ and NewDat=‘1 is illegal for an event driven transmit message.

The Message Objects for event driven transmit messages may be managed dynamically, several messages with different identifiers may share the same Message Object.

5.2 TTCAN Schedule Initialisation

The synchronisation to the TTCAN message schedule starts when the Operation Mode is switched from Configuration Mode to either Strictly Time Triggered Operation or to Event Synchronised Time Triggered Operation. All nodes will start with Cycle Time=0 at the beginning of their Trigger List, SyncSt will be 0 (out of synchronisation), and no transmission will be enabled with the exception of the Reference Message. Nodes in mode Event Synchronised Time Triggered Operation will ignore Tx_Ref_Trigger and Watch_Trigger and will use instead Tx_Ref_Trigger_Gap and Watch_Trigger_Gap until the first Reference Message decides whether a Gap is active.

5.2.1 Time Slaves

After configuration, a Time Slave will ignore its Watch_Trigger and Watch_Trigger_Gap when it did not receive any message before reaching the Watch_Triggers. When it reaches Initial_Watch_Trigger (not part of the Trigger List, defined as maximum of Cycle Time), IWT in the Interrupt Vector register is set, the FSE is frozen, and the Cycle Time will become invalid, but the node will still be able to take part in CAN bus communication (to give acknowledge or to send error flags). The first received Reference Message will restart FSE and Cycle Time.

When a Time Slave has received any message but the Reference Message before reaching the Watch_Triggers, it will assume a Fatal Error (Error Level 3), set WTr in the Interrupt Vector register, switch off its CAN bus output, and enter the Bus Monitoring Mode. In the Bus Monitoring Mode, it is still able to receive messages, but it cannot send any dominant bits and therefore cannot give acknowledge. The Fatal Error state can be left via a re-configuration.

When no error is encountered during synchronisation, the first Reference Message will put SyncST to Synchronising and the second will put it (depending on its Next_is_Gap bit) into In_Schedule or In_Gap, enabling all Tx_Triggers and Rx_Triggers.

5.2.2 Potential Time Masters

After configuration, a Potential Time Master will start the transmission of a Reference Message when it reaches its Tx_Ref_Trigger (or its Tx_Ref_Trigger_Gap when in mode Event Synchronised Time Triggered Operation). It will ignore its Watch_Trigger and Watch_Trigger_Gap when it did not receive any message or transmit the Reference Message successfully before reaching the Watch_Triggers (assumed reason: All other nodes still in

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Contents Robert Bosch GmbH User’s ManualCopyright Notice and Proprietary Information Conventions Scope References Terms and Abbreviations Functional Overview 2.2. Block Diagram Operating ModesChange Control Can Application Ttcan Schedule Initialisation Ttcan ConfigurationTtcan Message Handling List of FiguresChange History Change Control Current StatusConventions Helvetica boldTerm Meaning Functional Overview Ttcan CpuifcCan Message Transfer Operating Modes Software InitialisationTest Register addresses 0x0B & 0x0A Disabled Automatic RetransmissionTest Mode Ttcan =1 Loop Back combined with Silent Mode Loop Back ModeSoftware control of Pin Cantx No Message RAM ModeAddress Name Reset Value Ttcan Register Summary Hardware Reset DescriptionDAR CCEEIE SIEStatus Register addresses 0x03 No ErrorBit Timing Register addresses 0x07 Error Counter addresses 0x05Status Interrupts BRP Extension Register addresses 0x0D & 0x0C Arb IFx Command Mask RegistersDirection = Write Direction = Read IFx Command Request RegistersControl ClrIntPndMessage Number BusyIFx Message Buffer Registers IFx Mask RegistersMessage Object in the Message Memory IFx Message Control RegistersIFx Data a and Data B Registers Msk28-0 ID28-0Xtd Dir26/77 11.11.02 Interrupt Register addresses 0x09 Message Handler RegistersInterrupt Pending Registers Transmission Request RegistersNew Data Registers Trigger Number 2 IF1 Data B1 and B2 Registers for Trigger Memory AccessMessage Valid 1 Register Type TT Operation Mode Register addresses 0x29TimeMark At CycleCount mod MPr2-0TEW EecsRdlc CCM TT Interrupt Enable Register addresses 0x31Bark AppWdLGTE CELGTW SWERTO TUR Numerator Configuration Low Register addresses 0x57 TT Error Level Register addresses 0x3F & 0x3ETT Cycle Count Register addresses 0x3D & 0x3C TT StopWatch Register addresses 0x61 TUR Denominator Configuration Register addresses 0x59TUR Numerator Actual Registers addresses 0x5B & 0x5A Qgtp QCSEcal EgtfDET TMCECS SWSTMG EPE40/77 11.11.02 Data Transfer Between IFx Registers and Message RAM Internal can Message HandlingStart Transmission of Messages in Event Driven can CommunicationReception of Data Frame Acceptance Filtering of Received MessagesReception of Remote Frame Storing Received Messages in Fifo BuffersConfiguration of the Module Receive / Transmit Priority1 Configuration of the Bit Timing Sync PropSeg PhaseSeg1 PhaseSeg2Bit Time and Bit Rate Canclk input Nominal can Bit TimeBRP Propagation Time SegmentPhase Buffer Segments and Synchronisation Synchronisation on late and early Edges Filtering of Short Dominant Spikes 1.5 Configuration of the can Protocol Controller Oscillator Tolerance RangeCalculation of the Bit Timing Parameters Example for Bit Timing at high Baudrate 2 Configuration of the Message Memory Example for Bit Timing at low Baudrate2.2 Configuration of a Single Receive Object for Data Frames 2.1 Configuration of a Transmit Object for Data Frames2.3 Configuration of a Fifo Buffer Handling of Interrupts Can CommunicationUpdating a Transmit Object Reading Received Messages Changing a Transmit ObjectRequesting New Data for a Receive Object Reading from a Fifo BufferCPU Handling of a Fifo Buffer Interrupt Driven Ttcan Timing Ttcan ConfigurationMessage Scheduling TUR510 125000 32.5 100/12 529/17 Trigger Memory 63/77 11.11.02 Periodic Transmit Message Message ObjectsReference Message Potential Time Masters Event Driven Transmit MessageTime Slaves Message Transmission Ttcan Message Handling Message ReceptionPeriodic Messages Event Driven MessagesStopwatch Ttcan Gap ControlCycle Time and Global Time Synchronisation Previous RefMark Ttcan Interrupt and Error HandlingConfiguration Example Rdlc & TEW & CCM Register RemarkType & Msg & CycleCode RTO , TM , L2 , TTMode3 74/77 11.11.02 Customer Interface GenericInterface Canclk Canwaitb Timing of the Wait output signalBusy = ‘1’ Busy = ‘0’ Interrupt TimingEOF
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