Bosch Appliances TTCAN user manual Message Objects, Reference Message, Periodic Transmit Message

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TTCAN

User’s Manual

Revision 1.6

manual_about.fm

A typical Trigger List for a potential Time Master will begin with a number of Tx_Triggers and Rx_Triggers followed by the Tx_Ref_Trigger and the Watch_Trigger. For networks with Event Synchronised Time triggered Communication, this is followed by the Tx_Ref_Trigger_Gap and the Watch_Trigger_Gap. The Trigger List for a Time Slave will be the same but without the Tx_Ref_Trigger and the Tx_Ref_Trigger_Gap.

At the beginning of each Basic Cycle, that is at each reception or transmission of a Reference Message, the Trigger List will be processed starting with the first Trigger Memory word. The FSE looks for the first Trigger with a Cycle_Code that matches the current Cycle_Count. The FSE waits until Cycle Time reaches the Trigger’s Time_Mark and activates the Trigger. Afterwards the FSE looks for the next Trigger in the list with a Cycle_Code that matches the current Cycle_Count.

A Configuration Error is detected at the following conditions :

When the FSE comes to a Trigger in the list with a Cycle_Code that matches the current Cycle_Count but with a Time_Mark that is less than Cycle Time.

When the FSE comes to a Trigger in the list with a Cycle_Code that matches the current Cycle_Count but that is neither Tx_Trigger_Merged nor Tx_Trigger_Single and the previous active Trigger was a Tx_Trigger_Merged.

When the FSE of a node with TM=‘0’ encounters a Tx_Ref_Trigger or a Tx_Ref_Trigger_Gap.

When the Time_Mark of an Rx_Trigger is placed inside the Tx_Enable Window of a Tx_Trigger with a matching Cycle_Code or between a Tx_Trigger_Merged and another Tx_Trigger with a Cycle_Code matching the same Cycle_Count.

When the Time_Mark of an Rx_Trigger is placed near the Time_Mark of a Tx_Ref_Trigger and the Ref_Trigger_Offset causes a reversal of their sequential order measured in Cycle Time.

5.1.4 Message Objects

The Message Status Count MSC of each Message Object has to be initialised to 0. It can only be written in “Configuration Mode”. The configuration of Receive Objects for “Time Triggered Communication” is the same as for “Event driven Communication”, see chapter 4.2.2. Some differences exist for the configuration of the Reference Message and of Transmit Objects:

5.1.4.1 Reference Message

The first Message Object is reserved for the transmission or reception of the Reference Message. When a Reference Message is transmitted, the last three bits of the Identifier, the DLC, and the first data byte (TTCAN Level 1) or the first three data bytes (TTCAN Level 2) will be provided by the FSE, the rest of the Reference Message is provided by the first Message Object. The first Message Object requires the following configuration: The Identifier and the Data Length Code of the Reference Message including IDE bit, MsgVal=‘1’, NewDat=‘1’, TxRqst=‘0’, UMask=‘1’, EoB=‘1’, Dir=‘1’, MDir=‘0’. When the Reference Message uses an Extended Identifier, Msk=0x1FFFFFF8, else Msk=0x1FE3FFFF. The MSC of the first Message Object will not be updated.

5.1.4.2 Periodic Transmit Message

The Message Objects for periodic transmit messages may not be managed dynamically, each Tx_Trigger in the Trigger Memory points to a particular Message Object containing a specific message. There may be more than one Tx_Trigger for a given Message Object, if that Message Object contains a message that is to be transmitted more than once in a Basic Cycle or Matrix Cycle. The configuration has to define MsgVal=‘1’, RmtEn=‘0’, TxRqst=‘0’, UMask=‘0’, EoB=‘1’, Dir=‘1’, MDir=‘0’, MSC=0, the identifier, the IDE bit, and the DLC.

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Contents User’s Manual Robert Bosch GmbHCopyright Notice and Proprietary Information Change Control Functional Overview 2.2. Block Diagram Operating ModesConventions Scope References Terms and Abbreviations Can Application Ttcan Configuration Ttcan Schedule InitialisationTtcan Message Handling List of FiguresChange Control Current Status Change HistoryConventions Helvetica boldTerm Meaning Functional Overview Cpuifc TtcanOperating Modes Software Initialisation Can Message TransferTest Mode Disabled Automatic RetransmissionTest Register addresses 0x0B & 0x0A Ttcan =1 Loop Back Mode Loop Back combined with Silent ModeNo Message RAM Mode Software control of Pin CantxAddress Name Reset Value Hardware Reset Description Ttcan Register SummaryCCE DAREIE SIENo Error Status Register addresses 0x03Status Interrupts Error Counter addresses 0x05Bit Timing Register addresses 0x07 BRP Extension Register addresses 0x0D & 0x0C Direction = Write IFx Command Mask RegistersArb IFx Command Request Registers Direction = ReadControl ClrIntPndBusy Message NumberIFx Message Buffer Registers IFx Mask RegistersIFx Data a and Data B Registers IFx Message Control RegistersMessage Object in the Message Memory ID28-0 Msk28-0Xtd Dir26/77 11.11.02 Message Handler Registers Interrupt Register addresses 0x09New Data Registers Transmission Request RegistersInterrupt Pending Registers Message Valid 1 Register 2 IF1 Data B1 and B2 Registers for Trigger Memory AccessTrigger Number TT Operation Mode Register addresses 0x29 TypeTimeMark At CycleCount mod MPr2-0Rdlc EecsTEW TT Interrupt Enable Register addresses 0x31 CCMBark AppWdLCEL GTEGTW SWERTO TT Cycle Count Register addresses 0x3D & 0x3C TT Error Level Register addresses 0x3F & 0x3ETUR Numerator Configuration Low Register addresses 0x57 TUR Numerator Actual Registers addresses 0x5B & 0x5A TUR Denominator Configuration Register addresses 0x59TT StopWatch Register addresses 0x61 QCS QgtpEcal EgtfTMC DETECS SWSEPE TMG40/77 11.11.02 Internal can Message Handling Data Transfer Between IFx Registers and Message RAMTransmission of Messages in Event Driven can Communication StartAcceptance Filtering of Received Messages Reception of Data FrameReception of Remote Frame Storing Received Messages in Fifo BuffersReceive / Transmit Priority Configuration of the ModuleSync PropSeg PhaseSeg1 PhaseSeg2 1 Configuration of the Bit TimingBit Time and Bit Rate Canclk input Nominal can Bit TimePropagation Time Segment BRPPhase Buffer Segments and Synchronisation Synchronisation on late and early Edges Filtering of Short Dominant Spikes Oscillator Tolerance Range 1.5 Configuration of the can Protocol ControllerCalculation of the Bit Timing Parameters Example for Bit Timing at high Baudrate Example for Bit Timing at low Baudrate 2 Configuration of the Message Memory2.1 Configuration of a Transmit Object for Data Frames 2.2 Configuration of a Single Receive Object for Data Frames2.3 Configuration of a Fifo Buffer Can Communication Handling of InterruptsUpdating a Transmit Object Changing a Transmit Object Reading Received MessagesRequesting New Data for a Receive Object Reading from a Fifo BufferCPU Handling of a Fifo Buffer Interrupt Driven Ttcan Configuration Ttcan Timing510 125000 32.5 100/12 529/17 TURMessage Scheduling Trigger Memory 63/77 11.11.02 Reference Message Message ObjectsPeriodic Transmit Message Time Slaves Event Driven Transmit MessagePotential Time Masters Ttcan Message Handling Message Reception Message TransmissionPeriodic Messages Event Driven MessagesTtcan Gap Control StopwatchCycle Time and Global Time Synchronisation Ttcan Interrupt and Error Handling Previous RefMarkConfiguration Example Register Remark Rdlc & TEW & CCMType & Msg & CycleCode RTO , TM , L2 , TTMode3 74/77 11.11.02 Interface GenericCustomer Interface Timing of the Wait output signal Canclk CanwaitbBusy = ‘1’ Busy = ‘0’ Interrupt TimingEOF
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