Bosch Appliances TTCAN user manual Eecs, Rdlc, Tew

Page 31

TTCAN

User’s Manual

Revision 1.6

manual_about.fm

EECS	Enable External Clock Synchronisation
	one	TUR Conﬁguration (NumCfg only) may be updated during
		TTCAN operation.
	zero	TUR Conﬁguration may not be updated.
TTMode	TTCAN Operation Mode
	0x0	TTMode_0 Event driven CAN Communication (default mode).
	0x1	TTMode_1 Conﬁguration Mode.
	0x2	TTMode_2 Strictly Time Triggered Operation.
	0x3	TTMode_3 Event Synchronised Time Triggered Operation.

Note : The CPU may write to the TT Operation Mode register only during initialisation (Init and CCE are set). Conﬁguration Mode enables the write access to the other TTCAN conﬁguration regis- ters. The whole CAN module remains in initialisation mode while TTMode is TTMode_1, “Con- ﬁguration Mode”, even if Init is reset.

The following registers require TTMode_1 “Conﬁguration Mode” to be writable :

Name

Reset Value

Function

Trigger Memory Access

0x0000

Deﬁnes communication schedule

TT Operation Mode15-2

0x0000

Time mastership, clock control

TT Matrix Limits1

0x0000

Number of transmissions

TT Matrix Limits2

0x0000

Length of cycle components

TT Application Watchdog

0x0001

Watchdog service interval

TUR-NumeratorCfg

0x0000

Length of NTU

TUR-DenominatorCfg

0x1000

Length of NTU

Clock Control15-8

0x0000

Clock calibration, stopwatch, TMI

3.5.4 TT Matrix Limits1 Register (addresses 0x2B & 0x2A)

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

res

ETT

r

rw

ETT Expected Tx_Trigger

0x000-0xfFFExpected number of Tx_Triggers in one matrix cycle.

3.5.5 TT Matrix Limits2 Register (addresses 0x2D & 0x2C)

15		14	13	12	11	10	9	8	7	6		5	4	3	2	1	0
		RDLC				TEW			res						CCM

		rw				rw			r						rw
RDLC		Reference Message Data Length Code
		0x0			invalid value.
		0x1-0xF			DLC of Reference Message to transmit when Time Master.
TEW		Tx_Enable Window
		0x0-0xF			Length of Tx_Enable Window.

BOSCH

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11.11.02

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Contents Robert Bosch GmbH User’s ManualCopyright Notice and Proprietary Information Change Control Functional Overview 2.2. Block Diagram Operating ModesConventions Scope References Terms and Abbreviations Can Application List of Figures Ttcan ConfigurationTtcan Schedule Initialisation Ttcan Message HandlingHelvetica bold Change Control Current StatusChange History ConventionsTerm Meaning Functional Overview Ttcan CpuifcCan Message Transfer Operating Modes Software InitialisationTest Mode Disabled Automatic RetransmissionTest Register addresses 0x0B & 0x0A Ttcan =1 Loop Back combined with Silent Mode Loop Back ModeSoftware control of Pin Cantx No Message RAM ModeAddress Name Reset Value Ttcan Register Summary Hardware Reset DescriptionSIE CCEDAR EIEStatus Register addresses 0x03 No ErrorStatus Interrupts Error Counter addresses 0x05Bit Timing Register addresses 0x07 BRP Extension Register addresses 0x0D & 0x0C Direction = Write IFx Command Mask RegistersArb ClrIntPnd IFx Command Request RegistersDirection = Read ControlIFx Mask Registers BusyMessage Number IFx Message Buffer RegistersIFx Data a and Data B Registers IFx Message Control RegistersMessage Object in the Message Memory Dir ID28-0Msk28-0 Xtd26/77 11.11.02 Interrupt Register addresses 0x09 Message Handler Registers New Data Registers Transmission Request Registers Interrupt Pending Registers Message Valid 1 Register 2 IF1 Data B1 and B2 Registers for Trigger Memory AccessTrigger Number MPr2-0 TT Operation Mode Register addresses 0x29Type TimeMark At CycleCount modRdlc EecsTEW AppWdL TT Interrupt Enable Register addresses 0x31CCM BarkSWE CELGTE GTWRTO TT Cycle Count Register addresses 0x3D & 0x3C TT Error Level Register addresses 0x3F & 0x3ETUR Numerator Conﬁguration Low Register addresses 0x57 TUR Numerator Actual Registers addresses 0x5B & 0x5A TUR Denominator Conﬁguration Register addresses 0x59TT StopWatch Register addresses 0x61 Egtf QCSQgtp EcalSWS TMCDET ECSTMG EPE40/77 11.11.02 Data Transfer Between IFx Registers and Message RAM Internal can Message HandlingStart Transmission of Messages in Event Driven can CommunicationStoring Received Messages in Fifo Buffers Acceptance Filtering of Received MessagesReception of Data Frame Reception of Remote FrameConﬁguration of the Module Receive / Transmit PriorityCanclk input Nominal can Bit Time Sync PropSeg PhaseSeg1 PhaseSeg21 Conﬁguration of the Bit Timing Bit Time and Bit RateBRP Propagation Time SegmentPhase Buffer Segments and Synchronisation Synchronisation on late and early Edges Filtering of Short Dominant Spikes 1.5 Conﬁguration of the can Protocol Controller Oscillator Tolerance RangeCalculation of the Bit Timing Parameters Example for Bit Timing at high Baudrate 2 Conﬁguration of the Message Memory Example for Bit Timing at low Baudrate2.2 Conﬁguration of a Single Receive Object for Data Frames 2.1 Conﬁguration of a Transmit Object for Data Frames2.3 Conﬁguration of a Fifo Buffer Handling of Interrupts Can CommunicationUpdating a Transmit Object Reading from a Fifo Buffer Changing a Transmit ObjectReading Received Messages Requesting New Data for a Receive ObjectCPU Handling of a Fifo Buffer Interrupt Driven Ttcan Timing Ttcan Conﬁguration510 125000 32.5 100/12 529/17 TURMessage Scheduling Trigger Memory 63/77 11.11.02 Reference Message Message ObjectsPeriodic Transmit Message Time Slaves Event Driven Transmit MessagePotential Time Masters Event Driven Messages Ttcan Message Handling Message ReceptionMessage Transmission Periodic MessagesStopwatch Ttcan Gap ControlCycle Time and Global Time Synchronisation Previous RefMark Ttcan Interrupt and Error HandlingConﬁguration Example Rdlc & TEW & CCM Register RemarkType & Msg & CycleCode RTO , TM , L2 , TTMode3 74/77 11.11.02 Interface GenericCustomer Interface Interrupt Timing Timing of the Wait output signalCanclk Canwaitb Busy = ‘1’ Busy = ‘0’EOF