Bosch Appliances TTCAN user manual Can Communication, Handling of Interrupts

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TTCAN

User’s Manual

Revision 1.6

manual_about.fm

‘0’), it is programmed to ID28 - ID18, ID17 - ID0 can then be disregarded. When a Remote Frame with an 11-bit Identifier is received, ID17 - ID0 will be set to ‘0’.

The Data Length Code (DLC3-0) may be given by the application. When the Message Handler stores a Remote Frame in the Message Object, it will store the received Data Length Code. The data bytes of the Message Object will remain unchanged.

If the RxIE bit is set, the IntPnd bit will be set when a received Remote Frame is accepted and stored in the Message Object.

4.3 CAN Communication

When the initialisation is finished, the TTCAN module synchronises itself to the traffic on the CAN bus. It does an acceptance filtering on received messages and stored those frames that are accepted into the designated Message Objects. The application program has to update the data of the messages to be transmitted and has to enable and request their transmission. The transmission is requested automatically when a matching Remote Frame is received or in time triggered communication.

The application program reads messages that are received and accepted. Messages that are not read before the next messages is accepted for the same Message Object will be overwritten. The Message Objects of a FIFO buffer need to be read and cleared before the next batch of messages can be stored. Depending on the configuration, the messages may be read interrupt-driven, after polling of NewDat, or time triggered.

If one of the Interface Register sets is used only for reading of received messages its Command Mask Register may be kept constant at 0x7F, meaning that always the whole Message Object is transferred into the Interface Register set; NewDat and IntPnd are reset.

To update the data bytes of a message to be transmitted, the Command Mask Register should be set to 0x87 (all transmit messages in C_CAN emulation mode or event triggered message in arbitrating time window) or to 0x83 (time triggered message in exclusive time window).

Note : After the update of the Transmit Object, the Interface Register set will contain a copy of the actual contents of the object, including the part that had not been updated.

4.3.1 Handling of Interrupts

The TTCAN module provides several interrupt sources which share a common interrupt line. The common interrupt line to the CPU can be enabled/disabled by IE. The module’s interrupt sources can be enabled/disabled separately, by the TT Interrupt Enable Register, by the CAN Control Register bits SIE and EIE, or by the RxIE and TxIE bits of each Message Object. The source of a pending interrupt is shown by the CAN Interrupt Register.

The Status Interrupt and the TTCAN Interrupt have the highest priority. Among the message interrupts, the Message Object’ s interrupt priority decreases with increasing Message Number.

If several interrupts are pending, the CAN Interrupt Register will point to the pending interrupt with the highest priority, disregarding their chronological order. An interrupt remains pending until the CPU has cleared it.

A message interrupt is cleared by clearing the Message Object’s IntPnd bit. The Status Interrupt is cleared by reading the Status Register. The TTCAN Interrupt is cleared by reading the TT Interrupt Vector Register.

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Contents User’s Manual Robert Bosch GmbHCopyright Notice and Proprietary Information Conventions Scope References Terms and Abbreviations Functional Overview 2.2. Block Diagram Operating ModesChange Control Can Application Ttcan Configuration Ttcan Schedule InitialisationTtcan Message Handling List of FiguresChange Control Current Status Change HistoryConventions Helvetica boldTerm Meaning Functional Overview Cpuifc TtcanOperating Modes Software Initialisation Can Message TransferTest Register addresses 0x0B & 0x0A Disabled Automatic RetransmissionTest Mode Ttcan =1 Loop Back Mode Loop Back combined with Silent ModeNo Message RAM Mode Software control of Pin CantxAddress Name Reset Value Hardware Reset Description Ttcan Register SummaryCCE DAREIE SIENo Error Status Register addresses 0x03Bit Timing Register addresses 0x07 Error Counter addresses 0x05Status Interrupts BRP Extension Register addresses 0x0D & 0x0C Arb IFx Command Mask RegistersDirection = Write IFx Command Request Registers Direction = ReadControl ClrIntPndBusy Message NumberIFx Message Buffer Registers IFx Mask RegistersMessage Object in the Message Memory IFx Message Control RegistersIFx Data a and Data B Registers ID28-0 Msk28-0Xtd Dir26/77 11.11.02 Message Handler Registers Interrupt Register addresses 0x09Interrupt Pending Registers Transmission Request RegistersNew Data Registers Trigger Number 2 IF1 Data B1 and B2 Registers for Trigger Memory AccessMessage Valid 1 Register TT Operation Mode Register addresses 0x29 TypeTimeMark At CycleCount mod MPr2-0TEW EecsRdlc TT Interrupt Enable Register addresses 0x31 CCMBark AppWdLCEL GTEGTW SWERTO TUR Numerator Configuration Low Register addresses 0x57 TT Error Level Register addresses 0x3F & 0x3ETT Cycle Count Register addresses 0x3D & 0x3C TT StopWatch Register addresses 0x61 TUR Denominator Configuration Register addresses 0x59TUR Numerator Actual Registers addresses 0x5B & 0x5A QCS QgtpEcal EgtfTMC DETECS SWSEPE TMG40/77 11.11.02 Internal can Message Handling Data Transfer Between IFx Registers and Message RAMTransmission of Messages in Event Driven can Communication StartAcceptance Filtering of Received Messages Reception of Data FrameReception of Remote Frame Storing Received Messages in Fifo BuffersReceive / Transmit Priority Configuration of the ModuleSync PropSeg PhaseSeg1 PhaseSeg2 1 Configuration of the Bit TimingBit Time and Bit Rate Canclk input Nominal can Bit TimePropagation Time Segment BRPPhase Buffer Segments and Synchronisation Synchronisation on late and early Edges Filtering of Short Dominant Spikes Oscillator Tolerance Range 1.5 Configuration of the can Protocol ControllerCalculation of the Bit Timing Parameters Example for Bit Timing at high Baudrate Example for Bit Timing at low Baudrate 2 Configuration of the Message Memory2.1 Configuration of a Transmit Object for Data Frames 2.2 Configuration of a Single Receive Object for Data Frames2.3 Configuration of a Fifo Buffer Can Communication Handling of InterruptsUpdating a Transmit Object Changing a Transmit Object Reading Received MessagesRequesting New Data for a Receive Object Reading from a Fifo BufferCPU Handling of a Fifo Buffer Interrupt Driven Ttcan Configuration Ttcan TimingMessage Scheduling TUR510 125000 32.5 100/12 529/17 Trigger Memory 63/77 11.11.02 Periodic Transmit Message Message ObjectsReference Message Potential Time Masters Event Driven Transmit MessageTime Slaves Ttcan Message Handling Message Reception Message TransmissionPeriodic Messages Event Driven MessagesTtcan Gap Control StopwatchCycle Time and Global Time Synchronisation Ttcan Interrupt and Error Handling Previous RefMarkConfiguration Example Register Remark Rdlc & TEW & CCMType & Msg & CycleCode RTO , TM , L2 , TTMode3 74/77 11.11.02 Customer Interface GenericInterface Timing of the Wait output signal Canclk CanwaitbBusy = ‘1’ Busy = ‘0’ Interrupt TimingEOF
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