Bosch Appliances TTCAN user manual Configuration Example

Page 70

TTCAN

User’s Manual

Revision 1.6

manual_about.fm

The TT Interrupt Vector consists of four segments, each four bits long. Each of the bits of the

TTInterrupt Vector can be separately enabled by a corresponding bit in the TT Interrupt Enable register. Once a bit of the TT Interrupt Vector is set, it will remain set until the application program writes a ‘0’ to this bit.

The first segment consists of CfE, ApW, Wtr, and IWT. Each of these interrupts indicates a fatal error condition where the CAN communication is stopped. With the exception of IWT (see chapter 5.2), these error conditions require a re-configuration of the TTCAN module before the communication can be restarted.

The second segment consists of CEL, TxO, TxU, and GTE. Each of these interrupts indicates an error condition where the CAN communication is disturbed. If they are caused by a transient failure, e.g. by disturbance on the CAN bus, they will be handled by the TTCAN protocol’s failure handling and do not require intervention by the application program.

The third segment consists of Dis, GTW, SWE, and TMI. The first two interrupts are caused by Global Time events (Level 2 only) that require a reaction by the application program. The Stop Watch Event and the Time Mark Interrupt provide feedback to the application program when the application has requested the timing of external events or the notification on reaching a specific time. The Time Mark Interrupt can also be used to finish a Gap.

The fourth segment consists of Gap, CSM, SSM, and SBC. These interrupts provide a means to synchronise the application program to the communication schedule.

5.8 Configuration Example

This is a configuration example for a TTCAN system consisting of three nodes (M0, M1, and S0) operating in TTCAN level 2 at a bit rate of 1 MBit/s. All three nodes have a system clock frequency of 10 MHz, the network time unit NTU is 1 ∝s. Two nodes (M0 and M1) are potential time masters, the third node S0 is operating as a time slave.

 

0x00A0

0x0140

0x01E0

0x0280

0x0320

0x03E6

0x0540

0x2000

0x2200

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0

M0_Msg2

S0_Msg2

M1_Msg2

Merged_Arb_Win

 

 

 

 

 

 

 

 

 

 

 

 

 

1

S0_Msg3

S0_Msg2

M0_Msg3

M1_Msg3

Arb_Win1

Ref_Msg

Watch

Ref_Gap

Watch_Gap

 

 

 

 

 

 

2

M0_Msg2

S0_Msg2

M1_Msg2

Arb_Win2

M1_Msg4

 

 

 

 

 

 

 

 

 

 

 

 

 

 

3

S0_Msg3

S0_Msg2

M0_Msg3

M1_Msg3

Arb_Win3

 

 

 

 

 

 

 

 

 

 

 

 

 

 

The System Matrix consists of four Basic Cycles 0…3, each Basic Cycle has five transmission columns at Cycle Time 0x00A0, 0x0140, 0x01E0, 0x0280, and 0x320. The length of the Basic Cycle is 0x03E8 NTUs=1000∝s=1ms. M0 transmits the messages M0_Msg2 and M0_Msg3 in exclusive time windows. M1 transmits the messages M1_Msg2, M1_Msg3, and M1_Msg4 in exclusive time windows. S0 transmits the messages S0_Msg2 and S0_Msg3 in exclusive time windows. All nodes may transmit in the single or merged arbitrating time windows.

M0 checks whether M1_Msg2 and S0_Msg2 are received on time. M1 checks whether M0_Msg3 and S0_Msg3 are received on time. S0 checks whether M0_Msg2 and M1_Msg4 are received on time.

The messages in the arbitrating time windows are transmitted event-driven, there is no Rx_Trigger to check for their reception.

The time between the trigger for the Reference Message and the Watch_Trigger (and between Tx_Ref_Trigger_Gap and Watch_Trigger_Gap in case of a time gap) is long enough to allow for the retransmission of a disturbed Reference Message.

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Contents User’s Manual Robert Bosch GmbHCopyright Notice and Proprietary Information Change Control Functional Overview 2.2. Block Diagram Operating ModesConventions Scope References Terms and Abbreviations Can Application Ttcan Message Handling Ttcan ConfigurationTtcan Schedule Initialisation List of FiguresConventions Change Control Current StatusChange History Helvetica boldTerm Meaning Functional Overview Cpuifc TtcanOperating Modes Software Initialisation Can Message TransferTest Mode Disabled Automatic RetransmissionTest Register addresses 0x0B & 0x0A Ttcan =1 Loop Back Mode Loop Back combined with Silent ModeNo Message RAM Mode Software control of Pin CantxAddress Name Reset Value Hardware Reset Description Ttcan Register SummaryEIE CCEDAR SIENo Error Status Register addresses 0x03Status Interrupts Error Counter addresses 0x05Bit Timing Register addresses 0x07 BRP Extension Register addresses 0x0D & 0x0C Direction = Write IFx Command Mask RegistersArb Control IFx Command Request RegistersDirection = Read ClrIntPndIFx Message Buffer Registers BusyMessage Number IFx Mask RegistersIFx Data a and Data B Registers IFx Message Control RegistersMessage Object in the Message Memory Xtd ID28-0Msk28-0 Dir26/77 11.11.02 Message Handler Registers Interrupt Register addresses 0x09New Data Registers Transmission Request RegistersInterrupt Pending Registers Message Valid 1 Register 2 IF1 Data B1 and B2 Registers for Trigger Memory AccessTrigger Number TimeMark At CycleCount mod TT Operation Mode Register addresses 0x29Type MPr2-0Rdlc EecsTEW Bark TT Interrupt Enable Register addresses 0x31CCM AppWdLGTW CELGTE SWERTO TT Cycle Count Register addresses 0x3D & 0x3C TT Error Level Register addresses 0x3F & 0x3ETUR Numerator Configuration Low Register addresses 0x57 TUR Numerator Actual Registers addresses 0x5B & 0x5A TUR Denominator Configuration Register addresses 0x59TT StopWatch Register addresses 0x61 Ecal QCSQgtp EgtfECS TMCDET SWSEPE TMG40/77 11.11.02 Internal can Message Handling Data Transfer Between IFx Registers and Message RAMTransmission of Messages in Event Driven can Communication StartReception of Remote Frame Acceptance Filtering of Received MessagesReception of Data Frame Storing Received Messages in Fifo BuffersReceive / Transmit Priority Configuration of the ModuleBit Time and Bit Rate Sync PropSeg PhaseSeg1 PhaseSeg21 Configuration of the Bit Timing Canclk input Nominal can Bit TimePropagation Time Segment BRPPhase Buffer Segments and Synchronisation Synchronisation on late and early Edges Filtering of Short Dominant Spikes Oscillator Tolerance Range 1.5 Configuration of the can Protocol ControllerCalculation of the Bit Timing Parameters Example for Bit Timing at high Baudrate Example for Bit Timing at low Baudrate 2 Configuration of the Message Memory2.1 Configuration of a Transmit Object for Data Frames 2.2 Configuration of a Single Receive Object for Data Frames2.3 Configuration of a Fifo Buffer Can Communication Handling of InterruptsUpdating a Transmit Object Requesting New Data for a Receive Object Changing a Transmit ObjectReading Received Messages Reading from a Fifo BufferCPU Handling of a Fifo Buffer Interrupt Driven Ttcan Configuration Ttcan Timing510 125000 32.5 100/12 529/17 TURMessage Scheduling Trigger Memory 63/77 11.11.02 Reference Message Message ObjectsPeriodic Transmit Message Time Slaves Event Driven Transmit MessagePotential Time Masters Periodic Messages Ttcan Message Handling Message ReceptionMessage Transmission Event Driven MessagesTtcan Gap Control StopwatchCycle Time and Global Time Synchronisation Ttcan Interrupt and Error Handling Previous RefMarkConfiguration Example Register Remark Rdlc & TEW & CCMType & Msg & CycleCode RTO , TM , L2 , TTMode3 74/77 11.11.02 Interface GenericCustomer Interface Busy = ‘1’ Busy = ‘0’ Timing of the Wait output signalCanclk Canwaitb Interrupt TimingEOF
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