Bosch Appliances TTCAN user manual 74/77 11.11.02

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TTCAN

User’s Manual

Revision 1.6

manual_about.fm

The transmit message objects 5…6, to be transmitted in the arbitrating time windows, may be controlled dynamically or may be restricted to specific messages. Their identifiers should have a lower priority than the Reference Message or the periodic messages.

The Trigger Memory contains two triggers for the message object 5, so the transmission of the contents of this message object could start at the beginning of the merged arbitrating time window at 0x0280 or at the second trigger at 0x0320. The second trigger cannot start a second transmission if the first transmission was successful and the application did not request a second transmission.

After the configuration, the TTCAN module synchronises itself to the TTCAN message schedule. S0 will wait for the first Reference Message to finish its initialisation. M0 and M1 may reach Initialisation Watch Trigger and raise the IWT interrupt when one of them is the first node to finish configuration and does not get a dominant acknowledge bit for its transmitted Reference Message. In this case, the application program has to restart the TTCAN module by clearing the IWT bit.

In the configuration, the transmit message objects for the arbitrating time windows are not yet activated, so there will not be any transmissions in the arbitrating time windows until the application program loads the transmit message objects and requests the transmission.

The actual time master can control the synchronisation of the TTCAN network to external events, see chapter 3.5.23.

The nodes are configured to generate an event at their Time Mark interrupt outputs TMI at Cycle Time 0x0100, 0x0200, and 0x0300. These events are intended as triggers for time measurements and for the analysis of the message schedule.

The nodes are configured to capture their Global Time at an event at their stopwatch trigger inputs SWT. The nodes’ Global Time can be monitored and compared when all SWT inputs are triggered synchronously.

The application has to serve the Application Watchdog at least once in 65 ms, else the ApW interrupt is set and the TTCAN module enters TT Error Level “Fatal Error”, stopping all communication. This error requires a re-configuration. The Application Watchdog may be disabled during software development. The following modifications will disable the watchdog:

Line 1

: CAN Control to 00C1; Line 1a: CAN Test Register to 0001

Line 10

: Application Watchdog Limit to 0000

Line 99

: CAN Control to 0082

It might be useful for software development to copy (e.g. at the start of a Basic Cycle) the content of some of the TTCAN status registers (TT Master State, TT Error Level, TUR Numerator Actual, Clock Control, Gap Control, or Stop_Watch) into periodic messages that can be monitored with the usual CAN analysing tools.

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Contents User’s Manual Robert Bosch GmbHCopyright Notice and Proprietary Information Conventions Scope References Terms and Abbreviations Functional Overview 2.2. Block Diagram Operating ModesChange Control Can Application Ttcan Message Handling Ttcan ConfigurationTtcan Schedule Initialisation List of FiguresConventions Change Control Current StatusChange History Helvetica boldTerm Meaning Functional Overview Cpuifc TtcanOperating Modes Software Initialisation Can Message TransferTest Register addresses 0x0B & 0x0A Disabled Automatic RetransmissionTest Mode Ttcan =1 Loop Back Mode Loop Back combined with Silent ModeNo Message RAM Mode Software control of Pin CantxAddress Name Reset Value Hardware Reset Description Ttcan Register SummaryEIE CCEDAR SIENo Error Status Register addresses 0x03Bit Timing Register addresses 0x07 Error Counter addresses 0x05Status Interrupts BRP Extension Register addresses 0x0D & 0x0C Arb IFx Command Mask RegistersDirection = Write Control IFx Command Request RegistersDirection = Read ClrIntPndIFx Message Buffer Registers BusyMessage Number IFx Mask RegistersMessage Object in the Message Memory IFx Message Control RegistersIFx Data a and Data B Registers Xtd ID28-0Msk28-0 Dir26/77 11.11.02 Message Handler Registers Interrupt Register addresses 0x09Interrupt Pending Registers Transmission Request RegistersNew Data Registers Trigger Number 2 IF1 Data B1 and B2 Registers for Trigger Memory AccessMessage Valid 1 Register TimeMark At CycleCount mod TT Operation Mode Register addresses 0x29Type MPr2-0TEW EecsRdlc Bark TT Interrupt Enable Register addresses 0x31CCM AppWdLGTW CELGTE SWERTO TUR Numerator Configuration Low Register addresses 0x57 TT Error Level Register addresses 0x3F & 0x3ETT Cycle Count Register addresses 0x3D & 0x3C TT StopWatch Register addresses 0x61 TUR Denominator Configuration Register addresses 0x59TUR Numerator Actual Registers addresses 0x5B & 0x5A Ecal QCSQgtp EgtfECS TMCDET SWSEPE TMG40/77 11.11.02 Internal can Message Handling Data Transfer Between IFx Registers and Message RAMTransmission of Messages in Event Driven can Communication StartReception of Remote Frame Acceptance Filtering of Received MessagesReception of Data Frame Storing Received Messages in Fifo BuffersReceive / Transmit Priority Configuration of the ModuleBit Time and Bit Rate Sync PropSeg PhaseSeg1 PhaseSeg21 Configuration of the Bit Timing Canclk input Nominal can Bit TimePropagation Time Segment BRPPhase Buffer Segments and Synchronisation Synchronisation on late and early Edges Filtering of Short Dominant Spikes Oscillator Tolerance Range 1.5 Configuration of the can Protocol ControllerCalculation of the Bit Timing Parameters Example for Bit Timing at high Baudrate Example for Bit Timing at low Baudrate 2 Configuration of the Message Memory2.1 Configuration of a Transmit Object for Data Frames 2.2 Configuration of a Single Receive Object for Data Frames2.3 Configuration of a Fifo Buffer Can Communication Handling of InterruptsUpdating a Transmit Object Requesting New Data for a Receive Object Changing a Transmit ObjectReading Received Messages Reading from a Fifo BufferCPU Handling of a Fifo Buffer Interrupt Driven Ttcan Configuration Ttcan TimingMessage Scheduling TUR510 125000 32.5 100/12 529/17 Trigger Memory 63/77 11.11.02 Periodic Transmit Message Message ObjectsReference Message Potential Time Masters Event Driven Transmit MessageTime Slaves Periodic Messages Ttcan Message Handling Message ReceptionMessage Transmission Event Driven MessagesTtcan Gap Control StopwatchCycle Time and Global Time Synchronisation Ttcan Interrupt and Error Handling Previous RefMarkConfiguration Example Register Remark Rdlc & TEW & CCMType & Msg & CycleCode RTO , TM , L2 , TTMode3 74/77 11.11.02 Customer Interface GenericInterface Busy = ‘1’ Busy = ‘0’ Timing of the Wait output signalCanclk Canwaitb Interrupt TimingEOF
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