Bosch Appliances TTCAN user manual Type & Msg & CycleCode

Page 72

	TTCAN				User’s Manual			Revision 1.6

		Line	Ad	Register		Remark	M0	M1	S0


		37	1C	IF1 Message Control		EoB, DLC=8 (for arb. message)		0088

		38	10	IF1 Command Request		Arb_Msg1 for message object 5		0005

		39	10	IF1 Command Request		Arb_Msg2 for message object 6		0006

		40	10	IF1 Command Request		Arb_Msg3 for message object 7		0007

		41	10	IF1 Command Request		set objects 8…16 to not valid	0008…0010

		42	1A	IF1 Arbitration2		MsgVal, Dir=Rx, xx_Msgx id	8C48	8C0C	8C08

		43	1C	IF1 Message Control		EoB, DLC=8 (receive object)		0088

		44	10	IF1 Command Request		xx_Msgx in message object 17		0011

		45	1A	IF1 Arbitration2		MsgVal, Dir=Rx, xx_Msgx id	8C88	8C8C	8C50

		46	10	IF1 Command Request		xx_Msgx in message object 18		0012

		47	14	IF1 Mask1		all bits masked except Dir		0000

		48	16	IF1 Mask2				4000
		48	16	IF1 Mask2				4000

		49	18	IF1 Arbitration1		MsgVal, Dir =Tx/Rx		0000

		50	1A	IF1 Arbitration2				A000
		50	1A	IF1 Arbitration2				A000

		51	1C	IF1 Message Control		UMask, DLC=0, start of FIFO		1000

		52	10	IF1 Command Request		objects 19…31 are Rx-FIFO	0013…001F

		53	1C	IF1 Message Control		UMask, EoB, end of FIFO		1080

		54	10	IF1 Command Request		object 32 is end of Rx-FIFO		0020

		55	22	IF1 Message Data B1		Type & Msg & Cycle_Code	4202	D203	4303

		56	24	IF1 Message Data B2		Time_Mark	00A0	0138	00A0

		57	0E	Trigger Memory Access		write trigger 0		8000

		58	22	IF1 Message Data B1		Type & Msg & Cycle_Code	D200	4202	D102

		59	24	IF1 Message Data B2		Time_Mark	01D8	01E0	0138

		60	0E	Trigger Memory Access		write trigger 1		8001

		61	22	IF1 Message Data B1		Type & Msg & Cycle_Code	4303	D103	4200

		62	24	IF1 Message Data B2		Time_Mark	01E0	0278	0140

		63	0E	Trigger Memory Access		write trigger 2		8002

		64	22	IF1 Message Data B1		Type & Msg & Cycle_Code	D102	6504	6504

about.fm		65	24	IF1 Message Data B2		Time_Mark	0278	0280	0280

		66	0E	Trigger Memory Access		write trigger 3		8003
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manual
manual		67	22	IF1 Message Data B1		Type & Msg & Cycle_Code	6504	4303	4606
		67	22	IF1 Message Data B1		Type & Msg & Cycle_Code	6504	4303	4606

		68	24	IF1 Message Data B2		Time_Mark	0280	0280	0280

		69	0E	Trigger Memory Access		write trigger 4		8004

		70	22	IF1 Message Data B1		Type & Msg & Cycle_Code	4606	4606	4504

		71	24	IF1 Message Data B2		Time_Mark	0280	0280	0320

		72	0E	Trigger Memory Access		write trigger 5		8005

		73	22	IF1 Message Data B1		Type & Msg & Cycle_Code	4504	4504	4703

		74	24	IF1 Message Data B2		Time_Mark	0320	0320	0320

		75	0E	Trigger Memory Access		write trigger 6		8006

		76	22	IF1 Message Data B1		Type & Msg & Cycle_Code	4703	4703	D206

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11.11.02

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Contents User’s Manual Robert Bosch GmbHCopyright Notice and Proprietary Information Functional Overview 2.2. Block Diagram Operating Modes Change ControlConventions Scope References Terms and Abbreviations Can Application Ttcan Configuration Ttcan Schedule InitialisationTtcan Message Handling List of FiguresChange Control Current Status Change HistoryConventions Helvetica boldTerm Meaning Functional Overview Cpuifc TtcanOperating Modes Software Initialisation Can Message TransferDisabled Automatic Retransmission Test ModeTest Register addresses 0x0B & 0x0A Ttcan =1 Loop Back Mode Loop Back combined with Silent ModeNo Message RAM Mode Software control of Pin CantxAddress Name Reset Value Hardware Reset Description Ttcan Register SummaryCCE DAREIE SIENo Error Status Register addresses 0x03Error Counter addresses 0x05 Status InterruptsBit Timing Register addresses 0x07 BRP Extension Register addresses 0x0D & 0x0C IFx Command Mask Registers Direction = WriteArb IFx Command Request Registers Direction = ReadControl ClrIntPndBusy Message NumberIFx Message Buffer Registers IFx Mask RegistersIFx Message Control Registers IFx Data a and Data B RegistersMessage Object in the Message Memory ID28-0 Msk28-0Xtd Dir26/77 11.11.02 Message Handler Registers Interrupt Register addresses 0x09Transmission Request Registers New Data RegistersInterrupt Pending Registers 2 IF1 Data B1 and B2 Registers for Trigger Memory Access Message Valid 1 RegisterTrigger Number TT Operation Mode Register addresses 0x29 TypeTimeMark At CycleCount mod MPr2-0Eecs RdlcTEW TT Interrupt Enable Register addresses 0x31 CCMBark AppWdLCEL GTEGTW SWERTO TT Error Level Register addresses 0x3F & 0x3E TT Cycle Count Register addresses 0x3D & 0x3CTUR Numerator Conﬁguration Low Register addresses 0x57 TUR Denominator Conﬁguration Register addresses 0x59 TUR Numerator Actual Registers addresses 0x5B & 0x5ATT StopWatch Register addresses 0x61 QCS QgtpEcal EgtfTMC DETECS SWSEPE TMG40/77 11.11.02 Internal can Message Handling Data Transfer Between IFx Registers and Message RAMTransmission of Messages in Event Driven can Communication StartAcceptance Filtering of Received Messages Reception of Data FrameReception of Remote Frame Storing Received Messages in Fifo BuffersReceive / Transmit Priority Conﬁguration of the ModuleSync PropSeg PhaseSeg1 PhaseSeg2 1 Conﬁguration of the Bit TimingBit Time and Bit Rate Canclk input Nominal can Bit TimePropagation Time Segment BRPPhase Buffer Segments and Synchronisation Synchronisation on late and early Edges Filtering of Short Dominant Spikes Oscillator Tolerance Range 1.5 Conﬁguration of the can Protocol ControllerCalculation of the Bit Timing Parameters Example for Bit Timing at high Baudrate Example for Bit Timing at low Baudrate 2 Conﬁguration of the Message Memory2.1 Conﬁguration of a Transmit Object for Data Frames 2.2 Conﬁguration of a Single Receive Object for Data Frames2.3 Conﬁguration of a Fifo Buffer Can Communication Handling of InterruptsUpdating a Transmit Object Changing a Transmit Object Reading Received MessagesRequesting New Data for a Receive Object Reading from a Fifo BufferCPU Handling of a Fifo Buffer Interrupt Driven Ttcan Conﬁguration Ttcan TimingTUR 510 125000 32.5 100/12 529/17Message Scheduling Trigger Memory 63/77 11.11.02 Message Objects Reference MessagePeriodic Transmit Message Event Driven Transmit Message Time SlavesPotential Time Masters Ttcan Message Handling Message Reception Message TransmissionPeriodic Messages Event Driven MessagesTtcan Gap Control StopwatchCycle Time and Global Time Synchronisation Ttcan Interrupt and Error Handling Previous RefMarkConﬁguration Example Register Remark Rdlc & TEW & CCMType & Msg & CycleCode RTO , TM , L2 , TTMode3 74/77 11.11.02 Generic InterfaceCustomer Interface Timing of the Wait output signal Canclk CanwaitbBusy = ‘1’ Busy = ‘0’ Interrupt TimingEOF