Bosch Appliances TTCAN user manual Ttcan Gap Control, Stopwatch

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TTCAN

User’s Manual

Revision 1.6

manual_about.fm

Window, the retransmission may happen inside the same Window. The retransmission will not be started if NewDat is reset by the application program.

When a Message Object for event driven messages is managed dynamically, the contents of a Message Object may be changed at the same time the transmission is requested. In that case, any previous content of the Message Object that is not transmitted successfully is lost.

5.4 TTCAN Gap Control

In the mode Event Synchronised Time Triggered Operation, the TTCAN message schedule of the System Matrix may be interrupted by Gaps. In those Gaps, all transmissions are stopped and the CAN bus remains idle. A Gap is finished when the next Reference Message starts a new Basic Cycle. A Gap starts at the end of a Basic Cycle that itself was started by a Reference Message with the bit Next_is_Gap=‘1’, so the Gaps are initiated by the current Time Master.

The current Time Master has two options to initiate a Gap. A Gap can be initiated under software control when the application program writes NiG=‘1’ in the Gap Control register. A Gap can be initiated under hardware control when the application program enables (by writing EPE=‘1’) the EVENT_TRIGGER input pin. When a Reference Message is started and EPE is set, a high level at the EVENT_TRIGGER pin will cause Next_is_Gap=‘1’.

When a Potential Time Master is in SyncST In_Gap, it has three options to intentionally finish a Gap. Under software control, writing FGp=‘1’ or under Hardware control, a low level at the EVENT_TRIGGER pin will restart the schedule. The third option is a time triggered restart when the application program writes TMG=‘1, controlled by the Time Mark register. Neither of these options can cause a Basic Cycle to be interrupted with a Reference Message.

Any Potential Time Master will finish a Gap when it reaches its Tx_Ref_Trigger_Gap, assuming that the event to synchronise on did not occur in time.

In the mode Strictly Time Triggered Operation, the bit Next_is_Gap=‘1’ in the Reference Message will be ignored, as well as the EVENT_TRIGGER pin and the bits NiG, EoG, and TMG in the Gap Control register.

5.5 Stopwatch

Although the application program can read the Local Time, Cycle Time, or Global Time registers any time, the Stopwatch register offers the possibility to time external events without any action by the application program.

To enable the Stopwatch, the application program first has to define Local Time, Cycle Time, or Global Time as the Stopwatch source by writing SWS in the TT Clock Control Register. When SWS is > 0 and SWE in the TT Interrupt Vector register is ‘0’, the actual value of the time selected by SWS will be copied into Stop_Watch on the next rising edge of the STOP_WATCH_TRIGGER pin and SWE will be set to ‘1’.

After the application program has read Stop_Watch, it may enable the next Stopwatch timing by resetting SWE to ‘0’.

5.6 Local Time, Cycle Time, and Global Time and External Clock Synchronisation

The Local Time is a Cyclic Counter consisting of a 16-bit integer part and a 3-bit fractional part. The integer part (the “Macro Tick”) is incremented once each NTU. The fractional part

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Contents Robert Bosch GmbH User’s ManualCopyright Notice and Proprietary Information Change Control Functional Overview 2.2. Block Diagram Operating ModesConventions Scope References Terms and Abbreviations Can Application List of Figures Ttcan ConfigurationTtcan Schedule Initialisation Ttcan Message HandlingHelvetica bold Change Control Current StatusChange History ConventionsTerm Meaning Functional Overview Ttcan CpuifcCan Message Transfer Operating Modes Software InitialisationTest Mode Disabled Automatic RetransmissionTest Register addresses 0x0B & 0x0A Ttcan =1 Loop Back combined with Silent Mode Loop Back ModeSoftware control of Pin Cantx No Message RAM ModeAddress Name Reset Value Ttcan Register Summary Hardware Reset DescriptionSIE CCEDAR EIEStatus Register addresses 0x03 No ErrorStatus Interrupts Error Counter addresses 0x05Bit Timing Register addresses 0x07 BRP Extension Register addresses 0x0D & 0x0C Direction = Write IFx Command Mask RegistersArb ClrIntPnd IFx Command Request RegistersDirection = Read ControlIFx Mask Registers BusyMessage Number IFx Message Buffer RegistersIFx Data a and Data B Registers IFx Message Control RegistersMessage Object in the Message Memory Dir ID28-0Msk28-0 Xtd26/77 11.11.02 Interrupt Register addresses 0x09 Message Handler RegistersNew Data Registers Transmission Request RegistersInterrupt Pending Registers Message Valid 1 Register 2 IF1 Data B1 and B2 Registers for Trigger Memory AccessTrigger Number MPr2-0 TT Operation Mode Register addresses 0x29Type TimeMark At CycleCount modRdlc EecsTEW AppWdL TT Interrupt Enable Register addresses 0x31CCM BarkSWE CELGTE GTWRTO TT Cycle Count Register addresses 0x3D & 0x3C TT Error Level Register addresses 0x3F & 0x3ETUR Numerator Configuration Low Register addresses 0x57 TUR Numerator Actual Registers addresses 0x5B & 0x5A TUR Denominator Configuration Register addresses 0x59TT StopWatch Register addresses 0x61 Egtf QCSQgtp EcalSWS TMCDET ECSTMG EPE40/77 11.11.02 Data Transfer Between IFx Registers and Message RAM Internal can Message HandlingStart Transmission of Messages in Event Driven can CommunicationStoring Received Messages in Fifo Buffers Acceptance Filtering of Received MessagesReception of Data Frame Reception of Remote FrameConfiguration of the Module Receive / Transmit PriorityCanclk input Nominal can Bit Time Sync PropSeg PhaseSeg1 PhaseSeg21 Configuration of the Bit Timing Bit Time and Bit RateBRP Propagation Time SegmentPhase Buffer Segments and Synchronisation Synchronisation on late and early Edges Filtering of Short Dominant Spikes 1.5 Configuration of the can Protocol Controller Oscillator Tolerance RangeCalculation of the Bit Timing Parameters Example for Bit Timing at high Baudrate 2 Configuration of the Message Memory Example for Bit Timing at low Baudrate2.2 Configuration of a Single Receive Object for Data Frames 2.1 Configuration of a Transmit Object for Data Frames2.3 Configuration of a Fifo Buffer Handling of Interrupts Can CommunicationUpdating a Transmit Object Reading from a Fifo Buffer Changing a Transmit ObjectReading Received Messages Requesting New Data for a Receive ObjectCPU Handling of a Fifo Buffer Interrupt Driven Ttcan Timing Ttcan Configuration510 125000 32.5 100/12 529/17 TURMessage Scheduling Trigger Memory 63/77 11.11.02 Reference Message Message ObjectsPeriodic Transmit Message Time Slaves Event Driven Transmit MessagePotential Time Masters Event Driven Messages Ttcan Message Handling Message ReceptionMessage Transmission Periodic MessagesStopwatch Ttcan Gap ControlCycle Time and Global Time Synchronisation Previous RefMark Ttcan Interrupt and Error HandlingConfiguration Example Rdlc & TEW & CCM Register RemarkType & Msg & CycleCode RTO , TM , L2 , TTMode3 74/77 11.11.02 Interface GenericCustomer Interface Interrupt Timing Timing of the Wait output signalCanclk Canwaitb Busy = ‘1’ Busy = ‘0’EOF
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