Bosch Appliances TTCAN user manual IFx Message Control Registers, IFx Data a and Data B Registers

Page 24

TTCAN

User’s Manual

Revision 1.6

manual_about.fm

3.3.3.3 IFx Message Control Registers

IF1 Message Control Register

15

14

13

12

11

10

9

8

7

6 5 4

3 2 1 0

(addresses 0x1D & 0x1C)

 

 

 

 

 

 

 

 

 

 

NewDat

MsgLst

IntPnd

UMask

TxIE

RxIE

RmtEn

TxRqst

EoB

MSC2-0

DLC3-0

 

 

 

 

 

 

 

 

 

 

 

 

IF2 Message Control Register

NewDat

MsgLst

IntPnd

UMask

TxIE

RxIE

RmtEn

TxRqst

EoB

MSC2-0

DLC3-0

(addresses 0x4D & 0x4C)

 

 

 

 

 

 

 

 

 

 

 

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

 

 

 

 

 

 

 

 

 

 

 

 

 

3.3.3.4 IFx Data A and Data B Registers

The data bytes of CAN messages are stored in the IFx registers in the following order:

 

 

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

IF1 Message Data A1 (addresses 0x1F & 0x1E)

 

 

 

Data(1)

 

 

 

 

 

 

Data(0)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

IF1 Message Data A2 (addresses 0x21 & 0x20)

 

 

 

Data(3)

 

 

 

 

 

 

Data(2)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

IF1 Message Data B1 (addresses 0x23

& 0x22)

 

 

 

Data(5)

 

 

 

 

 

 

Data(4)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

IF1 Message Data B2 (addresses 0x25

& 0x24)

 

 

 

Data(7)

 

 

 

 

 

 

Data(6)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

IF2 Message Data A1 (addresses 0x4F

& 0x4E)

 

 

 

Data(1)

 

 

 

 

 

 

Data(0)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

IF2 Message Data A2 (addresses 0x51 & 0x50)

 

 

 

Data(3)

 

 

 

 

 

 

Data(2)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

IF2 Message Data B1 (addresses 0x53

& 0x52)

 

 

 

Data(5)

 

 

 

 

 

 

Data(4)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

IF2 Message Data B2 (addresses 0x55

& 0x54)

 

 

 

Data(7)

 

 

 

 

 

 

Data(6)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

rw

 

 

 

 

 

 

 

rw

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

In a CAN Data Frame, Data(0) is the first, Data(7) is the last byte to be transmitted or received. In CAN’s serial bit stream, the MSB of each byte will be transmitted first.

3.3.4 Message Object in the Message Memory

There are 32 Message Objects in the Message RAM. To avoid conflicts between CPU access to the Message RAM and CAN message reception and transmission, the CPU cannot directly access the Message Objects, these accesses are handled via the IFx Interface Registers.

Figure 7 gives an overview of the two structure of a Message Object.

Message Object

UMask

Msk28-0

MXtd

MDir

EoB

MSC2-0

NewDat

MsgLst

RxIE

TxIE

IntPnd

RmtEn

TxRqst

 

 

 

 

 

 

 

 

 

 

 

 

 

MsgVal

ID28-0

Xtd

Dir

DLC3-0

Data 0

Data 1

Data 2

Data 3

Data 4

Data 5

Data 6

Data 7

 

 

 

 

 

 

 

 

 

 

 

 

 

Figure 7: Structure of a Message Object in the Message Memory

MsgVal Message Valid

one The Message Object is configured and should be considered by the Mes- sage Handler.

zero The Message Object is ignored by the Message Handler.

Note : The CPU must reset the MsgVal bit of all unused Messages Objects during the initialization before it resets bit Init in the CAN Control Register. This bit must also be reset before the iden- tifier Id28-0, the control bits Xtd, Dir, or the Data Length Code DLC3-0are modified, or if the Messages Object is no longer required.

UMask Use Acceptance Mask

one Use Mask (Msk28-0, MXtd, and MDir) for acceptance filtering zero Mask ignored.

Note : If the UMask bit is set to one, the Message Object’s mask bits have to be programmed during initialization of the Message Object before MsgVal is set to one.

BOSCH

- 24/77 -

11.11.02

Page 23 Page 25
Image 24
Page 23 Page 25
Contents User’s Manual Robert Bosch GmbHCopyright Notice and Proprietary Information Functional Overview 2.2. Block Diagram Operating Modes Change ControlConventions Scope References Terms and Abbreviations Can Application Ttcan Configuration Ttcan Schedule InitialisationTtcan Message Handling List of FiguresChange Control Current Status Change HistoryConventions Helvetica boldTerm Meaning Functional Overview Cpuifc TtcanOperating Modes Software Initialisation Can Message TransferDisabled Automatic Retransmission Test ModeTest Register addresses 0x0B & 0x0A Ttcan =1 Loop Back Mode Loop Back combined with Silent ModeNo Message RAM Mode Software control of Pin CantxAddress Name Reset Value Hardware Reset Description Ttcan Register SummaryCCE DAREIE SIENo Error Status Register addresses 0x03Error Counter addresses 0x05 Status InterruptsBit Timing Register addresses 0x07 BRP Extension Register addresses 0x0D & 0x0C IFx Command Mask Registers Direction = Write Arb IFx Command Request Registers Direction = ReadControl ClrIntPndBusy Message NumberIFx Message Buffer Registers IFx Mask RegistersIFx Message Control Registers IFx Data a and Data B RegistersMessage Object in the Message Memory ID28-0 Msk28-0Xtd Dir26/77 11.11.02 Message Handler Registers Interrupt Register addresses 0x09Transmission Request Registers New Data RegistersInterrupt Pending Registers 2 IF1 Data B1 and B2 Registers for Trigger Memory Access Message Valid 1 RegisterTrigger Number TT Operation Mode Register addresses 0x29 TypeTimeMark At CycleCount mod MPr2-0Eecs RdlcTEW TT Interrupt Enable Register addresses 0x31 CCMBark AppWdLCEL GTEGTW SWERTO TT Error Level Register addresses 0x3F & 0x3E TT Cycle Count Register addresses 0x3D & 0x3CTUR Numerator Configuration Low Register addresses 0x57 TUR Denominator Configuration Register addresses 0x59 TUR Numerator Actual Registers addresses 0x5B & 0x5ATT StopWatch Register addresses 0x61 QCS QgtpEcal EgtfTMC DETECS SWSEPE TMG40/77 11.11.02 Internal can Message Handling Data Transfer Between IFx Registers and Message RAMTransmission of Messages in Event Driven can Communication StartAcceptance Filtering of Received Messages Reception of Data FrameReception of Remote Frame Storing Received Messages in Fifo BuffersReceive / Transmit Priority Configuration of the ModuleSync PropSeg PhaseSeg1 PhaseSeg2 1 Configuration of the Bit TimingBit Time and Bit Rate Canclk input Nominal can Bit TimePropagation Time Segment BRPPhase Buffer Segments and Synchronisation Synchronisation on late and early Edges Filtering of Short Dominant Spikes Oscillator Tolerance Range 1.5 Configuration of the can Protocol ControllerCalculation of the Bit Timing Parameters Example for Bit Timing at high Baudrate Example for Bit Timing at low Baudrate 2 Configuration of the Message Memory2.1 Configuration of a Transmit Object for Data Frames 2.2 Configuration of a Single Receive Object for Data Frames2.3 Configuration of a Fifo Buffer Can Communication Handling of InterruptsUpdating a Transmit Object Changing a Transmit Object Reading Received MessagesRequesting New Data for a Receive Object Reading from a Fifo BufferCPU Handling of a Fifo Buffer Interrupt Driven Ttcan Configuration Ttcan TimingTUR 510 125000 32.5 100/12 529/17Message Scheduling Trigger Memory 63/77 11.11.02 Message Objects Reference MessagePeriodic Transmit Message Event Driven Transmit Message Time SlavesPotential Time Masters Ttcan Message Handling Message Reception Message TransmissionPeriodic Messages Event Driven MessagesTtcan Gap Control StopwatchCycle Time and Global Time Synchronisation Ttcan Interrupt and Error Handling Previous RefMarkConfiguration Example Register Remark Rdlc & TEW & CCMType & Msg & CycleCode RTO , TM , L2 , TTMode3 74/77 11.11.02 Generic InterfaceCustomer Interface Timing of the Wait output signal Canclk CanwaitbBusy = ‘1’ Busy = ‘0’ Interrupt TimingEOF
Top Page Image Contents