Bosch Appliances TTCAN user manual 1 Configuration of the Bit Timing, Bit Time and Bit Rate

Page 45

TTCAN

User’s Manual

Revision 1.6

4.2.1 Configuration of the Bit Timing

Even if minor errors in the configuration of the CAN bit timing do not result in immediate failure, the performance of a CAN network can be reduced significantly.

In many cases, the CAN bit synchronisation will amend a faulty configuration of the CAN bit timing to such a degree that only occasionally an error frame is generated. In the case of arbitration however, when two or more CAN nodes simultaneously try to transmit a frame, a misplaced sample point may cause one of the transmitters to become error passive.

The analysis of such sporadic errors requires a detailed knowledge of the CAN bit synchronisation inside a CAN node and of the CAN nodes’ interaction on the CAN bus.

4.2.1.1 Bit Time and Bit Rate

CAN supports bit rates in the range of lower than 1 KBit/s up to 1000 kBit/s. Each member of the CAN network has its own clock generator, usually a quartz oscillator. The timing parameter of the bit time (i.e. the reciprocal of the bit rate) can be configured individually for each CAN node, creating a common bit rate even though the CAN nodes’ oscillator periods (fosc) may be different.

The frequencies of these oscillators are not absolutely stable, small variations are caused by changes in temperature or voltage and by deteriorating components. As long as the variations remain inside a specific oscillator tolerance range (df), the CAN nodes are able to compensate for the different bit rates by resynchronising to the bit stream.

According to the CAN specification, the bit time is divided into four segments (see figure 9). The Synchronisation Segment, the Propagation Time Segment, the Phase Buffer Segment 1, and the Phase Buffer Segment 2. Each segment consists of a specific, programmable number of time quanta (see Table 1). The length of the time quantum (tq), which is the basic time unit of the bit time, is defined by the CAN controller’s system clock fsys and the Baud Rate Prescaler (BRP): tq = BRP / fsys. The TTCAN’s system clock fsys is the frequency of its

CAN_CLK input.

Nominal CAN Bit Time

manual_about.fm

Sync_ Prop_Seg

Phase_Seg1

Phase_Seg2

 

Seg

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1 Time Quantum

 

( tq )

Sample Point

Figure 9: Bit Timing

The Synchronisation Segment Sync_Seg is that part of the bit time where edges of the CAN bus level are expected to occur; the distance between an edge that occurs outside of Sync_Seg and the Sync_Seg is called the phase error of that edge. The Propagation Time Segment Prop_Seg is intended to compensate for the physical delay times within the CAN network. The Phase Buffer Segments Phase_Seg1 and Phase_Seg2 surround the Sample Point. The (Re-)Synchronisation Jump Width (SJW) defines how far a resynchronisation may move the Sample Point inside the limits defined by the Phase Buffer Segments to compensate for edge phase errors.

BOSCH

- 45/77 -

11.11.02

Page 44 Page 46
Image 45
Page 44 Page 46
Contents Robert Bosch GmbH User’s ManualCopyright Notice and Proprietary Information Functional Overview 2.2. Block Diagram Operating Modes Change ControlConventions Scope References Terms and Abbreviations Can Application Ttcan Schedule Initialisation Ttcan ConfigurationTtcan Message Handling List of FiguresChange History Change Control Current StatusConventions Helvetica boldTerm Meaning Functional Overview Ttcan CpuifcCan Message Transfer Operating Modes Software InitialisationDisabled Automatic Retransmission Test ModeTest Register addresses 0x0B & 0x0A Ttcan =1 Loop Back combined with Silent Mode Loop Back ModeSoftware control of Pin Cantx No Message RAM ModeAddress Name Reset Value Ttcan Register Summary Hardware Reset DescriptionDAR CCEEIE SIEStatus Register addresses 0x03 No ErrorError Counter addresses 0x05 Status InterruptsBit Timing Register addresses 0x07 BRP Extension Register addresses 0x0D & 0x0C IFx Command Mask Registers Direction = WriteArb Direction = Read IFx Command Request RegistersControl ClrIntPndMessage Number BusyIFx Message Buffer Registers IFx Mask RegistersIFx Message Control Registers IFx Data a and Data B RegistersMessage Object in the Message Memory Msk28-0 ID28-0Xtd Dir26/77 11.11.02 Interrupt Register addresses 0x09 Message Handler RegistersTransmission Request Registers New Data RegistersInterrupt Pending Registers 2 IF1 Data B1 and B2 Registers for Trigger Memory Access Message Valid 1 RegisterTrigger Number Type TT Operation Mode Register addresses 0x29TimeMark At CycleCount mod MPr2-0Eecs RdlcTEW CCM TT Interrupt Enable Register addresses 0x31Bark AppWdLGTE CELGTW SWERTO TT Error Level Register addresses 0x3F & 0x3E TT Cycle Count Register addresses 0x3D & 0x3CTUR Numerator Configuration Low Register addresses 0x57 TUR Denominator Configuration Register addresses 0x59 TUR Numerator Actual Registers addresses 0x5B & 0x5ATT StopWatch Register addresses 0x61 Qgtp QCSEcal EgtfDET TMCECS SWSTMG EPE40/77 11.11.02 Data Transfer Between IFx Registers and Message RAM Internal can Message Handling Start Transmission of Messages in Event Driven can CommunicationReception of Data Frame Acceptance Filtering of Received MessagesReception of Remote Frame Storing Received Messages in Fifo BuffersConfiguration of the Module Receive / Transmit Priority1 Configuration of the Bit Timing Sync PropSeg PhaseSeg1 PhaseSeg2Bit Time and Bit Rate Canclk input Nominal can Bit TimeBRP Propagation Time SegmentPhase Buffer Segments and Synchronisation Synchronisation on late and early Edges Filtering of Short Dominant Spikes 1.5 Configuration of the can Protocol Controller Oscillator Tolerance RangeCalculation of the Bit Timing Parameters Example for Bit Timing at high Baudrate 2 Configuration of the Message Memory Example for Bit Timing at low Baudrate2.2 Configuration of a Single Receive Object for Data Frames 2.1 Configuration of a Transmit Object for Data Frames2.3 Configuration of a Fifo Buffer Handling of Interrupts Can CommunicationUpdating a Transmit Object Reading Received Messages Changing a Transmit ObjectRequesting New Data for a Receive Object Reading from a Fifo BufferCPU Handling of a Fifo Buffer Interrupt Driven Ttcan Timing Ttcan ConfigurationTUR 510 125000 32.5 100/12 529/17Message Scheduling Trigger Memory 63/77 11.11.02 Message Objects Reference MessagePeriodic Transmit Message Event Driven Transmit Message Time SlavesPotential Time Masters Message Transmission Ttcan Message Handling Message ReceptionPeriodic Messages Event Driven MessagesStopwatch Ttcan Gap ControlCycle Time and Global Time Synchronisation Previous RefMark Ttcan Interrupt and Error HandlingConfiguration Example Rdlc & TEW & CCM Register RemarkType & Msg & CycleCode RTO , TM , L2 , TTMode3 74/77 11.11.02 Generic InterfaceCustomer Interface Canclk Canwaitb Timing of the Wait output signalBusy = ‘1’ Busy = ‘0’ Interrupt TimingEOF
Top Page Image Contents