Bosch Appliances TTCAN user manual Address Name Reset Value

Page 15

TTCAN

User’s Manual

Revision 1.6

3. Programmer’s Model

The TTCAN module allocates an address space of 256 bytes. The registers are organized as 16-bit registers, with the high byte at the odd address and the low byte at the even address.

The two sets of interface registers (IF1 and IF2) control the CPU access to the Message RAM. They buffer the data to be transferred to and from the RAM, avoiding conflicts between CPU accesses and message reception/transmission.

 

Address

Name

Reset Value

Note

 

 

 

 

 

 

 

 

 

 

 

CAN Base+0x00

CAN Control Register

0x0001

CAN config register

 

 

 

 

 

 

CAN Base+0x02

Status Register

0x0000

CAN status register

 

 

 

 

 

 

CAN Base+0x04

Error Counter

0x0000

CAN status register

 

 

 

 

 

 

CAN Base+0x06

Bit Timing Register

0x2301

CAN config reg., req. CCE

 

 

 

 

 

 

CAN Base+0x08

Interrupt Register

0x0000

CAN status register

 

 

 

 

 

 

CAN Base+0x0A

Test Register

0x00 & 0br0000000 1)

CAN appl. reg., req. Test

 

CAN Base+0x0C

BRP Extension Register

0x0000

CAN config reg., req. CCE

 

 

 

 

 

 

CAN Base+0x0E

Trigger Memory Access

0x0000

TTCAN config register

 

 

 

 

 

 

CAN Base+0x10

IF1 Command Request

0x0001

CAN appl. IF1 Register Set

 

 

 

 

 

 

CAN Base+0x12

IF1 Command Mask

0x0000

 

 

 

 

 

 

 

CAN Base+0x14

IF1 Mask 1

0xFFFF

 

 

 

 

 

 

 

CAN Base+0x16

IF1 Mask 2

0xFFFF

 

 

 

 

 

 

 

CAN Base+0x18

IF1 Arbitration 1

0x0000

 

 

 

 

 

 

 

CAN Base+0x1A

IF1 Arbitration2

0x0000

 

 

 

 

 

 

 

CAN Base+0x1C

IF1 Message Control

0x0000

 

 

 

 

 

 

 

CAN Base+0x1E

IF1 Data A 1

0x0000

 

 

 

 

 

 

 

CAN Base+0x20

IF1 Data A 2

0x0000

 

 

 

 

 

 

 

CAN Base+0x22

IF1 Data B 1

0x0000

 

 

 

 

 

 

 

CAN Base+0x24

IF1 Data B 2

0x0000

 

 

 

 

 

 

 

CAN Base+0x26

— reserved

— 2)

 

 

CAN Base+0x28

TT Operation Mode

0x0000

TTCAN config register

 

 

 

 

 

 

CAN Base+0x2A

TT Matrix Limits1

0x0000

TTCAN config register

 

 

 

 

 

 

CAN Base+0x2C

TT Matrix Limits2

0x0000

TTCAN config register

 

 

 

 

 

 

CAN Base+0x2E

TT Application Watchdog

0x0001

TTCAN config register

 

 

 

 

 

 

CAN Base+0x30

TT Interrupt Enable

0x0000

TTCAN appl. register

about.fm

 

 

 

 

CAN Base+0x32

TT Interrupt Vector

0x0000

TTCAN status register

 

 

 

 

 

 

manual

CAN Base+0x34

TT Global Time

0x0000

TTCAN status register

 

 

 

 

CAN Base+0x36

TT Cycle Time

0x0000

TTCAN status register

 

 

 

 

 

 

 

CAN Base+0x38

TT Local Time

0x0000

TTCAN status register

 

 

 

 

 

 

CAN Base+0x3A

TT Master State

0x0000

TTCAN status register

 

 

 

 

 

 

CAN Base+0x3C

TT Cycle Count

0x003F

TTCAN status register

 

 

 

 

 

 

CAN Base+0x3E

TT Error Level

0x0000

TTCAN status register

 

 

 

 

 

 

CAN Base+0x40

IF2 Command Request

0x0001

CAN appl. IF2 Register Set

 

 

 

 

 

 

CAN Base+0x42

IF2 Command Mask

0x0000

 

 

 

 

 

 

 

CAN Base+0x44

IF2 Mask 1

0xFFFF

 

 

 

 

 

 

 

CAN Base+0x46

IF2 Mask 2

0xFFFF

 

 

 

 

 

 

 

 

 

 

 

1) r signifies the actual value of the CAN_RX pin.

 

 

 

2) Reserved bits are read as ’0’ except for IFx Mask 2 Register where they are read as ’1’

BOSCH

- 15/77 -

11.11.02

Page 14 Page 16
Image 15
Page 14 Page 16
Contents Robert Bosch GmbH User’s ManualCopyright Notice and Proprietary Information Functional Overview 2.2. Block Diagram Operating Modes Change ControlConventions Scope References Terms and Abbreviations Can Application List of Figures Ttcan ConfigurationTtcan Schedule Initialisation Ttcan Message HandlingHelvetica bold Change Control Current StatusChange History ConventionsTerm Meaning Functional Overview Ttcan CpuifcCan Message Transfer Operating Modes Software InitialisationDisabled Automatic Retransmission Test ModeTest Register addresses 0x0B & 0x0A Ttcan =1 Loop Back combined with Silent Mode Loop Back ModeSoftware control of Pin Cantx No Message RAM ModeAddress Name Reset Value Ttcan Register Summary Hardware Reset DescriptionSIE CCEDAR EIEStatus Register addresses 0x03 No ErrorError Counter addresses 0x05 Status InterruptsBit Timing Register addresses 0x07 BRP Extension Register addresses 0x0D & 0x0C IFx Command Mask Registers Direction = WriteArb ClrIntPnd IFx Command Request RegistersDirection = Read ControlIFx Mask Registers BusyMessage Number IFx Message Buffer RegistersIFx Message Control Registers IFx Data a and Data B RegistersMessage Object in the Message Memory Dir ID28-0Msk28-0 Xtd26/77 11.11.02 Interrupt Register addresses 0x09 Message Handler RegistersTransmission Request Registers New Data RegistersInterrupt Pending Registers 2 IF1 Data B1 and B2 Registers for Trigger Memory Access Message Valid 1 RegisterTrigger Number MPr2-0 TT Operation Mode Register addresses 0x29Type TimeMark At CycleCount modEecs RdlcTEW AppWdL TT Interrupt Enable Register addresses 0x31CCM BarkSWE CELGTE GTWRTO TT Error Level Register addresses 0x3F & 0x3E TT Cycle Count Register addresses 0x3D & 0x3CTUR Numerator Configuration Low Register addresses 0x57 TUR Denominator Configuration Register addresses 0x59 TUR Numerator Actual Registers addresses 0x5B & 0x5ATT StopWatch Register addresses 0x61 Egtf QCSQgtp EcalSWS TMCDET ECSTMG EPE40/77 11.11.02 Data Transfer Between IFx Registers and Message RAM Internal can Message HandlingStart Transmission of Messages in Event Driven can CommunicationStoring Received Messages in Fifo Buffers Acceptance Filtering of Received MessagesReception of Data Frame Reception of Remote FrameConfiguration of the Module Receive / Transmit PriorityCanclk input Nominal can Bit Time Sync PropSeg PhaseSeg1 PhaseSeg21 Configuration of the Bit Timing Bit Time and Bit RateBRP Propagation Time SegmentPhase Buffer Segments and Synchronisation Synchronisation on late and early Edges Filtering of Short Dominant Spikes 1.5 Configuration of the can Protocol Controller Oscillator Tolerance RangeCalculation of the Bit Timing Parameters Example for Bit Timing at high Baudrate 2 Configuration of the Message Memory Example for Bit Timing at low Baudrate2.2 Configuration of a Single Receive Object for Data Frames 2.1 Configuration of a Transmit Object for Data Frames2.3 Configuration of a Fifo Buffer Handling of Interrupts Can CommunicationUpdating a Transmit Object Reading from a Fifo Buffer Changing a Transmit ObjectReading Received Messages Requesting New Data for a Receive ObjectCPU Handling of a Fifo Buffer Interrupt Driven Ttcan Timing Ttcan ConfigurationTUR 510 125000 32.5 100/12 529/17Message Scheduling Trigger Memory 63/77 11.11.02 Message Objects Reference MessagePeriodic Transmit Message Event Driven Transmit Message Time SlavesPotential Time Masters Event Driven Messages Ttcan Message Handling Message ReceptionMessage Transmission Periodic MessagesStopwatch Ttcan Gap ControlCycle Time and Global Time Synchronisation Previous RefMark Ttcan Interrupt and Error HandlingConfiguration Example Rdlc & TEW & CCM Register RemarkType & Msg & CycleCode RTO , TM , L2 , TTMode3 74/77 11.11.02 Generic InterfaceCustomer Interface Interrupt Timing Timing of the Wait output signalCanclk Canwaitb Busy = ‘1’ Busy = ‘0’EOF
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