Bosch Appliances TTCAN user manual Epe, Tmg

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Event Pin Enable one

zero

Time Mark Gap one

zero

Finish Gap one

zero

Now is Gap one

zero

Gap Herald one

zero

Next is Gap one

zero

TTCAN

User’s Manual

Revision 1.6

manual_about.fm

3.5.22 TT Time Mark Register (addresses 0x6D & 0x6C)

15		14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								TMark

				rw									rw
TMark		Time Mark

0x0000-0xFFFFAn interrupt is generated when the time base indicated by TMC (Cycle Time, Local Time, or Global Time) has the same value as Time Mark.

Note : The Time Mark register can only be written while the time mark interrupt is disabled by TMC = 0.

3.5.23 TT Gap Control Register (addresses 0x6F & 0x6E)

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			res					EPE	res	TMG	FGp	res	Gap	GpH	NiG

			r					rw	r	rw	rw	r	r	r	rw

EPE

The EVENT_TRIGGER pin controls the Gaps.

The application program controls the Gaps.

TMG

The next Reference Message is started when the Time Mark

Interrupt TMI becomes active.

The bit is reset automatically at each Reference Message.

FGp

The next Reference Message is started immediately when Gap = ‘1’ or else at the next Tx_Ref_Trigger. This bit is set in TTMODE_3 by the CPU, by a Time Mark Interrupt if TMG = ‘1’, or by EVENT_TRIGGER pin = ‘0’ if EPE = ‘1’.

The bit is reset automatically at each Reference Message.

Gap

The Gap time after the Basic Cycle has started and TTMODE_3. No Gap in Schedule, this bit is reset automatically at each Refer- ence Message and in nodes that are time slaves.

GpH

Next_is_Gap = ‘1’ in Reference Message and TTMODE_3.

No Gap announced, this bit is reset automatically at each Refer- ence Message with Next_is_Gap = ‘0’.

NiG

Next_is_Gap = ‘1’ will be transmitted in next Reference Mes- sage(s). This bit can only be set by the CPU in a node that is the actual time master operating in TTMODE_3.

No action. The bit is reset automatically when any Reference

Message transmitted by another node is received.

The time master writes NiG to ‘1’ to initiate a Gap. The Next_is_Gap bit will be transmitted as ‘1’ in the next Reference Message. As soon as that Reference Message is completed, the GpH bit will announce the Gap to the time master as well as to the time slaves. The current

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Contents Robert Bosch GmbH User’s ManualCopyright Notice and Proprietary Information Functional Overview 2.2. Block Diagram Operating Modes Change ControlConventions Scope References Terms and Abbreviations Can Application List of Figures Ttcan ConfigurationTtcan Schedule Initialisation Ttcan Message HandlingHelvetica bold Change Control Current StatusChange History ConventionsTerm Meaning Functional Overview Ttcan CpuifcCan Message Transfer Operating Modes Software InitialisationDisabled Automatic Retransmission Test ModeTest Register addresses 0x0B & 0x0A Ttcan =1 Loop Back combined with Silent Mode Loop Back ModeSoftware control of Pin Cantx No Message RAM ModeAddress Name Reset Value Ttcan Register Summary Hardware Reset DescriptionSIE CCEDAR EIEStatus Register addresses 0x03 No ErrorError Counter addresses 0x05 Status InterruptsBit Timing Register addresses 0x07 BRP Extension Register addresses 0x0D & 0x0C IFx Command Mask Registers Direction = WriteArb ClrIntPnd IFx Command Request RegistersDirection = Read ControlIFx Mask Registers BusyMessage Number IFx Message Buffer RegistersIFx Message Control Registers IFx Data a and Data B RegistersMessage Object in the Message Memory Dir ID28-0Msk28-0 Xtd26/77 11.11.02 Interrupt Register addresses 0x09 Message Handler RegistersTransmission Request Registers New Data RegistersInterrupt Pending Registers 2 IF1 Data B1 and B2 Registers for Trigger Memory Access Message Valid 1 RegisterTrigger Number MPr2-0 TT Operation Mode Register addresses 0x29Type TimeMark At CycleCount modEecs RdlcTEW AppWdL TT Interrupt Enable Register addresses 0x31CCM BarkSWE CELGTE GTWRTO TT Error Level Register addresses 0x3F & 0x3E TT Cycle Count Register addresses 0x3D & 0x3CTUR Numerator Conﬁguration Low Register addresses 0x57 TUR Denominator Conﬁguration Register addresses 0x59 TUR Numerator Actual Registers addresses 0x5B & 0x5ATT StopWatch Register addresses 0x61 Egtf QCSQgtp EcalSWS TMCDET ECSTMG EPE40/77 11.11.02 Data Transfer Between IFx Registers and Message RAM Internal can Message HandlingStart Transmission of Messages in Event Driven can CommunicationStoring Received Messages in Fifo Buffers Acceptance Filtering of Received MessagesReception of Data Frame Reception of Remote FrameConﬁguration of the Module Receive / Transmit PriorityCanclk input Nominal can Bit Time Sync PropSeg PhaseSeg1 PhaseSeg21 Conﬁguration of the Bit Timing Bit Time and Bit RateBRP Propagation Time SegmentPhase Buffer Segments and Synchronisation Synchronisation on late and early Edges Filtering of Short Dominant Spikes 1.5 Conﬁguration of the can Protocol Controller Oscillator Tolerance RangeCalculation of the Bit Timing Parameters Example for Bit Timing at high Baudrate 2 Conﬁguration of the Message Memory Example for Bit Timing at low Baudrate2.2 Conﬁguration of a Single Receive Object for Data Frames 2.1 Conﬁguration of a Transmit Object for Data Frames2.3 Conﬁguration of a Fifo Buffer Handling of Interrupts Can CommunicationUpdating a Transmit Object Reading from a Fifo Buffer Changing a Transmit ObjectReading Received Messages Requesting New Data for a Receive ObjectCPU Handling of a Fifo Buffer Interrupt Driven Ttcan Timing Ttcan ConﬁgurationTUR 510 125000 32.5 100/12 529/17Message Scheduling Trigger Memory 63/77 11.11.02 Message Objects Reference MessagePeriodic Transmit Message Event Driven Transmit Message Time SlavesPotential Time Masters Event Driven Messages Ttcan Message Handling Message ReceptionMessage Transmission Periodic MessagesStopwatch Ttcan Gap ControlCycle Time and Global Time Synchronisation Previous RefMark Ttcan Interrupt and Error HandlingConﬁguration Example Rdlc & TEW & CCM Register RemarkType & Msg & CycleCode RTO , TM , L2 , TTMode3 74/77 11.11.02 Generic InterfaceCustomer Interface Interrupt Timing Timing of the Wait output signalCanclk Canwaitb Busy = ‘1’ Busy = ‘0’EOF