Bosch Appliances TTCAN user manual Internal can Message Handling

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TTCAN

User’s Manual

Revision 1.6

manual_about.fm

4. CAN Application

The TTCAN module can emulate a C_CAN module in ordinary event driven ISO 11898-1 CAN communication. C_CAN software can also be used for the TTCAN, provided that the TTCAN’s application watchdog is disabled in the configuration phase, as described in chapter 2.3.4.2.

The registers of the TTCAN module are subdivided into three classes: configuration registers, status registers, and application registers. The configuration registers are used only in the initialisation of the module. The application and status registers provide access to the CAN messages and give information on the CAN communication, interfacing between the internal message handling and the application program.

4.1 Internal CAN Message Handling

The Message Handler FSM controls the data transfer between the Rx/Tx Shift Register of the CAN Core, the Message RAM and the IFx Registers, performing the following tasks:

•Data Transfer from IFx Registers to the Message RAM.

•Data Transfer from Message RAM to the IFx Registers.

•Data Transfer from Message RAM to CAN_Core (messages to be transmitted).

•Data Transfer from CAN_Core to the Acceptance Filtering unit.

•Scanning of Message RAM for a matching Message Object (acceptance filtering).

•Data Transfer from CAN_Core to the Message RAM (received messages).

•Handling of TxRqst flags.

•Handling of interrupts.

4.1.1Data Transfer Between IFx Registers and Message RAM

There are two sets of IFx Registers. Each set of IFx Registers consists of Command Registers, controlling the data transfer, and Message Buffer Registers, containing the Message Object.

The Command Request Register addresses the desired Message Object in the Message RAM, the respective Command Mask Register specifies whether a complete Message Object or only parts of it will be transferred. The data transfer is initiated by writing to the Command Request Register.

Due to the structure of the Message RAM, it is not possible to change single bits/bytes of one Message Object, it is always necessary to access a complete Message Object in the Message RAM. Therefore the data transfer from the IFx Registers to the Message RAM requires the Message Handler FSM to perform a read-modify-write cycle. First those parts of the Message Object that are not to be changed are read from the Message RAM into the Message Buffer Registers, and then the complete contents of the Message Buffer Registers are written into the Message Object.

After the partial write of a Message Object, that Message Buffer Registers that are not selected in the Command Mask Register will be set to the actual contents of the selected Message Object.

After the partial read of a Message Object, that Message Buffer Registers that are not selected in the Command Mask Register will be left unchanged.

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11.11.02

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Contents Robert Bosch GmbH User’s ManualCopyright Notice and Proprietary Information Conventions Scope References Terms and Abbreviations Functional Overview 2.2. Block Diagram Operating ModesChange Control Can Application Ttcan Schedule Initialisation Ttcan ConfigurationTtcan Message Handling List of FiguresChange History Change Control Current StatusConventions Helvetica boldTerm Meaning Functional Overview Ttcan CpuifcCan Message Transfer Operating Modes Software InitialisationTest Register addresses 0x0B & 0x0A Disabled Automatic RetransmissionTest Mode Ttcan =1 Loop Back combined with Silent Mode Loop Back ModeSoftware control of Pin Cantx No Message RAM ModeAddress Name Reset Value Ttcan Register Summary Hardware Reset DescriptionDAR CCEEIE SIEStatus Register addresses 0x03 No ErrorBit Timing Register addresses 0x07 Error Counter addresses 0x05Status Interrupts BRP Extension Register addresses 0x0D & 0x0C Arb IFx Command Mask RegistersDirection = Write Direction = Read IFx Command Request RegistersControl ClrIntPndMessage Number BusyIFx Message Buffer Registers IFx Mask RegistersMessage Object in the Message Memory IFx Message Control RegistersIFx Data a and Data B Registers Msk28-0 ID28-0Xtd Dir26/77 11.11.02 Interrupt Register addresses 0x09 Message Handler RegistersInterrupt Pending Registers Transmission Request RegistersNew Data Registers Trigger Number 2 IF1 Data B1 and B2 Registers for Trigger Memory AccessMessage Valid 1 Register Type TT Operation Mode Register addresses 0x29TimeMark At CycleCount mod MPr2-0TEW EecsRdlc CCM TT Interrupt Enable Register addresses 0x31Bark AppWdLGTE CELGTW SWERTO TUR Numerator Configuration Low Register addresses 0x57 TT Error Level Register addresses 0x3F & 0x3ETT Cycle Count Register addresses 0x3D & 0x3C TT StopWatch Register addresses 0x61 TUR Denominator Configuration Register addresses 0x59TUR Numerator Actual Registers addresses 0x5B & 0x5A Qgtp QCSEcal EgtfDET TMCECS SWSTMG EPE40/77 11.11.02 Data Transfer Between IFx Registers and Message RAM Internal can Message HandlingStart Transmission of Messages in Event Driven can CommunicationReception of Data Frame Acceptance Filtering of Received MessagesReception of Remote Frame Storing Received Messages in Fifo BuffersConfiguration of the Module Receive / Transmit Priority1 Configuration of the Bit Timing Sync PropSeg PhaseSeg1 PhaseSeg2Bit Time and Bit Rate Canclk input Nominal can Bit TimeBRP Propagation Time SegmentPhase Buffer Segments and Synchronisation Synchronisation on late and early Edges Filtering of Short Dominant Spikes 1.5 Configuration of the can Protocol Controller Oscillator Tolerance RangeCalculation of the Bit Timing Parameters Example for Bit Timing at high Baudrate 2 Configuration of the Message Memory Example for Bit Timing at low Baudrate2.2 Configuration of a Single Receive Object for Data Frames 2.1 Configuration of a Transmit Object for Data Frames2.3 Configuration of a Fifo Buffer Handling of Interrupts Can CommunicationUpdating a Transmit Object Reading Received Messages Changing a Transmit ObjectRequesting New Data for a Receive Object Reading from a Fifo BufferCPU Handling of a Fifo Buffer Interrupt Driven Ttcan Timing Ttcan ConfigurationMessage Scheduling TUR510 125000 32.5 100/12 529/17 Trigger Memory 63/77 11.11.02 Periodic Transmit Message Message ObjectsReference Message Potential Time Masters Event Driven Transmit MessageTime Slaves Message Transmission Ttcan Message Handling Message ReceptionPeriodic Messages Event Driven MessagesStopwatch Ttcan Gap ControlCycle Time and Global Time Synchronisation Previous RefMark Ttcan Interrupt and Error HandlingConfiguration Example Rdlc & TEW & CCM Register RemarkType & Msg & CycleCode RTO , TM , L2 , TTMode3 74/77 11.11.02 Customer Interface GenericInterface Canclk Canwaitb Timing of the Wait output signalBusy = ‘1’ Busy = ‘0’ Interrupt TimingEOF
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