Bosch Appliances TTCAN user manual Generic, Customer Interface

Page 75

TTCAN

User’s Manual

Revision 1.6

manual_about.fm

6. CPU Interface

The interface of the TTCAN module consist of two parts (see figure 21). The Generic Interface which is a fixed part of the TTCAN module and the Customer Interface which can be adapted to the customers requirements.

Clock

Customer

CAN_CLK

Generic

 

 

 

 

Reset

Interface

CAN_RESET

Interface

RD_STATUS_REG_LOW

 

 

 

 

 

 

 

 

DB_W

 

 

 

 

(generic parameter)

 

 

 

 

CAN_WR_B

 

WR_<regx>_HIGH

 

Buffers

 

 

Control

 

Address

WR_<regx>_LOW

 

 

CAN_SELECT

Decode

Address(7:0)

Data Bus

CAN_ADDR

 

<regx>_HIGH_DIN

 

 

 

Control

 

 

<regx>_LOW_DIN

DataIN

 

CAN_DATA_IN

MUX

 

 

 

 

 

DataOUT

 

CAN_DATA_OUT

 

regx

 

 

 

Interrupt

Drivers

 

 

regy

 

 

 

 

 

 

 

 

CAN_INT

(optional output)

 

 

 

CAN_WAIT_B

 

 

 

 

Figure 21: Structure of the module interface

 

 

6.1 Customer Interface

The purpose of the Customer Interface is to adapt the timings of the module-external signals to the timing requirements of the module and to buffer / drive the external signals. Number and names of the module ports depend on the Customer Interface used with the actual implementation.

The Customer Interface also supplies the clock and reset signals for the module.

8 MHz is the minimum clock frequency required to operate the TTCAN module with a bit rate of 1 MBit/s. The maximum clock frequency is dependent on synthesis constraints and on the technology which is used for synthesis. The read / write timing of the TTCAN module depends on the Customer Interface used with the actual implementation.

Up to now three different Customer Interfaces are available for the TTCAN module. Two 16-bit interfaces to the AMBA APB bus from ARM and an 8-bit interface for the Motorola HC08 controller. A detailed description of these interfaces can be found in the Module Integration Guide, also describing how to build new Customer Interfaces for other CPUs.

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Contents Robert Bosch GmbH User’s ManualCopyright Notice and Proprietary Information Functional Overview 2.2. Block Diagram Operating Modes Change ControlConventions Scope References Terms and Abbreviations Can Application List of Figures Ttcan ConfigurationTtcan Schedule Initialisation Ttcan Message HandlingHelvetica bold Change Control Current StatusChange History ConventionsTerm Meaning Functional Overview Ttcan CpuifcCan Message Transfer Operating Modes Software InitialisationDisabled Automatic Retransmission Test ModeTest Register addresses 0x0B & 0x0A Ttcan =1 Loop Back combined with Silent Mode Loop Back ModeSoftware control of Pin Cantx No Message RAM ModeAddress Name Reset Value Ttcan Register Summary Hardware Reset DescriptionSIE CCEDAR EIEStatus Register addresses 0x03 No ErrorError Counter addresses 0x05 Status InterruptsBit Timing Register addresses 0x07 BRP Extension Register addresses 0x0D & 0x0C IFx Command Mask Registers Direction = WriteArb ClrIntPnd IFx Command Request RegistersDirection = Read ControlIFx Mask Registers BusyMessage Number IFx Message Buffer RegistersIFx Message Control Registers IFx Data a and Data B RegistersMessage Object in the Message Memory Dir ID28-0Msk28-0 Xtd26/77 11.11.02 Interrupt Register addresses 0x09 Message Handler RegistersTransmission Request Registers New Data RegistersInterrupt Pending Registers 2 IF1 Data B1 and B2 Registers for Trigger Memory Access Message Valid 1 RegisterTrigger Number MPr2-0 TT Operation Mode Register addresses 0x29Type TimeMark At CycleCount modEecs RdlcTEW AppWdL TT Interrupt Enable Register addresses 0x31CCM BarkSWE CELGTE GTWRTO TT Error Level Register addresses 0x3F & 0x3E TT Cycle Count Register addresses 0x3D & 0x3CTUR Numerator Configuration Low Register addresses 0x57 TUR Denominator Configuration Register addresses 0x59 TUR Numerator Actual Registers addresses 0x5B & 0x5ATT StopWatch Register addresses 0x61 Egtf QCSQgtp EcalSWS TMCDET ECSTMG EPE40/77 11.11.02 Data Transfer Between IFx Registers and Message RAM Internal can Message HandlingStart Transmission of Messages in Event Driven can CommunicationStoring Received Messages in Fifo Buffers Acceptance Filtering of Received MessagesReception of Data Frame Reception of Remote FrameConfiguration of the Module Receive / Transmit PriorityCanclk input Nominal can Bit Time Sync PropSeg PhaseSeg1 PhaseSeg21 Configuration of the Bit Timing Bit Time and Bit RateBRP Propagation Time SegmentPhase Buffer Segments and Synchronisation Synchronisation on late and early Edges Filtering of Short Dominant Spikes 1.5 Configuration of the can Protocol Controller Oscillator Tolerance RangeCalculation of the Bit Timing Parameters Example for Bit Timing at high Baudrate 2 Configuration of the Message Memory Example for Bit Timing at low Baudrate2.2 Configuration of a Single Receive Object for Data Frames 2.1 Configuration of a Transmit Object for Data Frames2.3 Configuration of a Fifo Buffer Handling of Interrupts Can CommunicationUpdating a Transmit Object Reading from a Fifo Buffer Changing a Transmit ObjectReading Received Messages Requesting New Data for a Receive ObjectCPU Handling of a Fifo Buffer Interrupt Driven Ttcan Timing Ttcan ConfigurationTUR 510 125000 32.5 100/12 529/17Message Scheduling Trigger Memory 63/77 11.11.02 Message Objects Reference MessagePeriodic Transmit Message Event Driven Transmit Message Time SlavesPotential Time Masters Event Driven Messages Ttcan Message Handling Message ReceptionMessage Transmission Periodic MessagesStopwatch Ttcan Gap ControlCycle Time and Global Time Synchronisation Previous RefMark Ttcan Interrupt and Error HandlingConfiguration Example Rdlc & TEW & CCM Register RemarkType & Msg & CycleCode RTO , TM , L2 , TTMode3 74/77 11.11.02 Generic InterfaceCustomer Interface Interrupt Timing Timing of the Wait output signalCanclk Canwaitb Busy = ‘1’ Busy = ‘0’EOF
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