Bosch Appliances TTCAN user manual Message Handler Registers, Interrupt Register addresses 0x09

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TTCAN

User’s Manual

Revision 1.6

manual_about.fm

Data 0 1st data byte of a CAN Data Frame

Data 1 2nd data byte of a CAN Data Frame

Data 2 3rd data byte of a CAN Data Frame

Data 3 4th data byte of a CAN Data Frame

Data 4 5th data byte of a CAN Data Frame

Data 5 6th data byte of a CAN Data Frame

Data 6 7th data byte of a CAN Data Frame

Data 7 8th data byte of a CAN Data Frame

Note : Byte Data 0 is the first data byte shifted into the shift register of the CAN Core during a recep- tion, byte Data 7 is the last. When the Message Handler stores a Data Frame, it will write all the eight data bytes into a Message Object. If the Data Length Code is less than 8, the remaining bytes of the Message Object will be overwritten by non specified values .

3.4 Message Handler Registers

All Message Handler registers are read-only. Their contents (TxRqst, NewDat, IntPnd, and MsgVal bits of each Message Object and the Interrupt Identifier) is status information provided by the Message Handler FSM.

3.4.1 Interrupt Register (addresses 0x09 & 0x08)

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

 

 

 

 

IntId15-8

 

 

 

 

 

 

IntId7-0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

r

 

 

 

 

 

 

 

r

 

 

 

IntId15-0Interrupt Identifier (the number here indicates the source of the interrupt)

 

 

 

 

 

0x0000

 

 

No interrupt is pending.

 

 

 

 

 

 

 

 

 

 

0x0001-0x0020

Number of Message Object which caused the interrupt.

 

 

 

 

 

0x0021-0x3FFF

unused.

 

 

 

 

 

 

 

 

 

 

 

 

 

0x4000

 

 

TTCAN Interrupt.

 

 

 

 

 

 

 

 

 

 

 

0x4001-0x7FFF

unused.

 

 

 

 

 

 

 

 

 

 

 

 

 

0x8000

 

 

Status Interrupt.

 

 

 

 

 

 

 

 

 

 

 

0x8001-0xBFFF

unused.

 

 

 

 

 

 

 

 

 

 

 

 

 

0xC000

 

 

TTCAN Interrupt and Status Interrupt.

 

 

 

 

0xC001-0xFFFF unused.

If several interrupts are pending, the CAN Interrupt Register will point to the pending interrupt with the highest priority, disregarding their chronological order. An interrupt remains pending until the CPU has cleared it. If IntId is different from 0x0000 and IE is set, the interrupt line to the CPU, IRQ_B, is active. The interrupt line remains active until IntId is back to value 0x0000 (the cause of the interrupt is reset) or until IE is reset.

The Status Interrupt has the highest priority. Among the message interrupts, the Message Object’s interrupt priority decreases with increasing message number.

A message interrupt is cleared by clearing the Message Object’s IntPnd bit. The Status Interrupt is cleared by reading the Status Register. The TTCAN Interrupt is cleared by reading the TTCAN Interrupt Vector Register.

BOSCH

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11.11.02

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Contents Robert Bosch GmbH User’s ManualCopyright Notice and Proprietary Information Functional Overview 2.2. Block Diagram Operating Modes Change ControlConventions Scope References Terms and Abbreviations Can Application List of Figures Ttcan ConfigurationTtcan Schedule Initialisation Ttcan Message HandlingHelvetica bold Change Control Current StatusChange History ConventionsTerm Meaning Functional Overview Ttcan CpuifcCan Message Transfer Operating Modes Software InitialisationDisabled Automatic Retransmission Test ModeTest Register addresses 0x0B & 0x0A Ttcan =1 Loop Back combined with Silent Mode Loop Back ModeSoftware control of Pin Cantx No Message RAM ModeAddress Name Reset Value Ttcan Register Summary Hardware Reset DescriptionSIE CCEDAR EIEStatus Register addresses 0x03 No ErrorError Counter addresses 0x05 Status InterruptsBit Timing Register addresses 0x07 BRP Extension Register addresses 0x0D & 0x0C IFx Command Mask Registers Direction = WriteArb ClrIntPnd IFx Command Request RegistersDirection = Read ControlIFx Mask Registers BusyMessage Number IFx Message Buffer RegistersIFx Message Control Registers IFx Data a and Data B RegistersMessage Object in the Message Memory Dir ID28-0Msk28-0 Xtd26/77 11.11.02 Interrupt Register addresses 0x09 Message Handler RegistersTransmission Request Registers New Data RegistersInterrupt Pending Registers 2 IF1 Data B1 and B2 Registers for Trigger Memory Access Message Valid 1 RegisterTrigger Number MPr2-0 TT Operation Mode Register addresses 0x29Type TimeMark At CycleCount modEecs RdlcTEW AppWdL TT Interrupt Enable Register addresses 0x31CCM BarkSWE CELGTE GTWRTO TT Error Level Register addresses 0x3F & 0x3E TT Cycle Count Register addresses 0x3D & 0x3CTUR Numerator Configuration Low Register addresses 0x57 TUR Denominator Configuration Register addresses 0x59 TUR Numerator Actual Registers addresses 0x5B & 0x5ATT StopWatch Register addresses 0x61 Egtf QCSQgtp EcalSWS TMCDET ECSTMG EPE40/77 11.11.02 Data Transfer Between IFx Registers and Message RAM Internal can Message HandlingStart Transmission of Messages in Event Driven can CommunicationStoring Received Messages in Fifo Buffers Acceptance Filtering of Received MessagesReception of Data Frame Reception of Remote FrameConfiguration of the Module Receive / Transmit PriorityCanclk input Nominal can Bit Time Sync PropSeg PhaseSeg1 PhaseSeg21 Configuration of the Bit Timing Bit Time and Bit RateBRP Propagation Time SegmentPhase Buffer Segments and Synchronisation Synchronisation on late and early Edges Filtering of Short Dominant Spikes 1.5 Configuration of the can Protocol Controller Oscillator Tolerance RangeCalculation of the Bit Timing Parameters Example for Bit Timing at high Baudrate 2 Configuration of the Message Memory Example for Bit Timing at low Baudrate2.2 Configuration of a Single Receive Object for Data Frames 2.1 Configuration of a Transmit Object for Data Frames2.3 Configuration of a Fifo Buffer Handling of Interrupts Can CommunicationUpdating a Transmit Object Reading from a Fifo Buffer Changing a Transmit ObjectReading Received Messages Requesting New Data for a Receive ObjectCPU Handling of a Fifo Buffer Interrupt Driven Ttcan Timing Ttcan ConfigurationTUR 510 125000 32.5 100/12 529/17Message Scheduling Trigger Memory 63/77 11.11.02 Message Objects Reference MessagePeriodic Transmit Message Event Driven Transmit Message Time SlavesPotential Time Masters Event Driven Messages Ttcan Message Handling Message ReceptionMessage Transmission Periodic MessagesStopwatch Ttcan Gap ControlCycle Time and Global Time Synchronisation Previous RefMark Ttcan Interrupt and Error HandlingConfiguration Example Rdlc & TEW & CCM Register RemarkType & Msg & CycleCode RTO , TM , L2 , TTMode3 74/77 11.11.02 Generic InterfaceCustomer Interface Interrupt Timing Timing of the Wait output signalCanclk Canwaitb Busy = ‘1’ Busy = ‘0’EOF
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