Fujitsu MB86617A manuals
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139 pages 599.54 Kb
LSI Specification MB86617A Rev.1.0 Fujitsu VLSI for DTV MB86617A LSI Specification 2 Contents 3 iii 6 Chapter 1 Overview LSI Specification MB86617A 7 Chapter 2 Features 8 Chapter 3 Chip Block 9 3.1. Block Diagram <<Normal Operation Mode 10 <<Asynchronous Transmit FIFO Extended Mode 11 <<Asynchronous Receive FIFO Extended Mode 12 3.2. Function of Each Block <<PHY Layer Control Circuit <<LINK Layer Control Circuit <<TSP IC Interface <<CP IC Interface <<Data Bridge 13 Chapter 4 Pin Assignment LSI Specification MB86617A 14 4.1. Pin Assignment The following diagram shows the MB86617A pin assignment. MB86617 FPT-176P-M03 15 4.2. Corresponding Table of MB86617A Pin 16 4.3. Outline Drawing of Package 17 Chapter 5 Pin Function 18 5.1. IEEE1394 Interface 19 5.2. Isochronous Interface 21 5.4. MPU Interface 22 5.5. Other Pins 23 5.6. Power/GND Pin 24 Chapter 6 Internal Register 32 7.1. M ode-control Register 34 7.2. flag & status Register 37 7.4. interrupt-factor Indicate Register/interrupt-mask Setting Register 38 7.5. Receive Acknowledge Indicate Register 39 7.6. A-buffer Data Port Receive/Transmit 40 7.7. TSP Transmit Information Setting Register [A] 42 7.8. TSP Transmit Information Setting Register [B] 44 7.9. Transmit Offset Setting Register [A] 45 7.10. Transmit Offset Setting Register [B] 46 7.11. TSP Receive Information Setting Register 51 7.14. TSP Status Register 53 7.15. Data Bridge Transmit Information Setting Register 1 [A] 54 7.16. Data Bridge Transmit Information Setting Register 2 [A] 55 7.17. Data Bridge Transmit Information Setting Register 3 [B] 56 7.18. Data Bridge Transmit Information Setting Register 4 [B] 57 7.19. Data Bridge Receive Information Setting Register 58 7.20. Transmit Packet Link/Split Setting Register 60 7.21. Late Packet Decision Range Setting Register [A] LSI Specification MB86617A 61 7.22. Late Packet Decision Range Setting Register [B] 62 7.23. Receive Isochronous Packet Header Indicate Register 1 [A] 63 7.24. Receive Isochronous Packet Header Indicate Register 2 [A] 64 7.25. Receive Isochronous Packet Header Indicate Register 3 [B] 65 7.26. Receive Isochronous Packet Header Indicate Register 4 [B] LSI Specification MB86617A 66 7.27. FIFO Reset Setting Register 67 7.28. Data Bridge Transmit/Receive Status Register [A] 70 7.29. Data Bridge Transmit/Receive Status Register [B] 73 7.30. Isochronous Channel Monitor Register 74 7.31. Cycle-timer-monitor Indicate Register 75 7.32. Ping Time Monitor Register 76 7.33. PHY/LINK Register/Address Setting Register 77 7.34. PHY/LINK Register Access Port 78 7.35. Revision Indicate Register 79 7.36. Transmit CGMS/TSCH Indicate Register [A] 80 7.37. Transmit CGMS/TSCH Indicate Register [B] 81 7.38. Transmit CGMS/TSCH Indicate Status Register 83 7.39. Transmit EMI/OE Setting Register 86 8.1. PHY/LINK Register Table 88 8.2. Physical register #00 (read) 89 8.3. Physical register #01 (read/write) 90 8.4. Physical register #02 (read) 91 8.5. Physical register #03 (read) 92 8.6. Physical register #04 (read/write) 93 8.7. Physical register #05 (read/write) 95 8.8. Physical register #07, 08, 09 (read) 96 8.9. Physical register #0A, 0B, 0C (read/write) 97 8.10. Physical register #0D, 0E, 0F (read/write) 98 8.11. Physical register #10 (read) 99 8.12. Physical register #11, 12, 13 (read) LSI Specification MB86617A 100 8.13. Physical register #14, 15, 16 (read) << Description of Eac h Bit 101 8.14. Physical register #17, 18, 19, 1A, 1B, 1C, 1D, 1E (read/write ) 102 8.15. Link register #00 (read/write) 103 8.16. Link register #01 (read/write) Link Register#00 is the register that sets this node to perform as cycle master. 104 8.17. Link register #02 (read/write) 105 8.18. Link register #03 (read/write) 106 Chapter 9 Instruction 107 9.1. Instruction Code Table LSI Specification MB86617A 108 9.2. Description of Each Instruction << Start sleep (01 h) << Remove sleep (02 h) << Asynchronous Receive (03 h) << Remove busy mode (04 h) << Send PHY packet (21 h) 109 LSI Specification MB86617A << Asynchronous Send (31 h) << Data -FIFO init (63h) 111 Chapter 10 Interrupt 112 10.1. Interrupt-factor Indicator Register & interrupt-mask Setting Register 113 10.2. Interrupt 114 10.3. Description of Interrupt 117 Chapter 11 Operation 118 11.1. Initialization 119 11.2. Self-ID Packet Receiving 125 11.3. Asynchronous Packet Transmitting << Flow chart before storing transmitting data into Asynchronous transmit FIFO 126 LSI Specification MB86617A << Flow chart after storing transmitting data into Asynchronous transmit FIFO 127 11.4. Asynchronous Packet Receiving 130 11.5. Isochronous Packet Transmitting 133 11.6. Isochronous Packet Receiving 135 Chapter 12 System Configuration 136 12.1. Recommended Connection for 1934 Port (for one port) 137 12.2 138 12.3. Recommended Connection for Build-in PLL Loop Filter FIL RF 139 12.4. Configuration of Feedback Circuit at Crystal Oscillator
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