Fujitsu MB86617A manual Fifo Reset Setting Register

LSI Specification MB86617A

7.27. FIFO Reset Setting Register

FIFO reset setting register sets force reset of bridge and each FIFO.

AD

R/W

Bit

Bit

Bit

Bit

Bit

Bit

Bit

Bit

Bit

Bit

Bit

Bit

Bit

Bit

Bit

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

resetT

reset

reset-

reset

reset

4Ch

R/W

reset-B

SP

BRG

-

-

-

-

-

TSP

BRG

-

-

-

-

-

FIFO-

FIFO-

A

FIFO-

FIFO-

B

B

A

A

Initial Value

‘0’

‘0’

‘0’

‘0’

‘0’

‘0’

‘0’

‘0’

‘0’

‘0’

‘0’

‘0’

‘0’

‘0’

‘0’

‘0’

BIT

Bit Name

Action

Value

Function

Read/

0

Releases forced reset of bridge-Bch.

15

reset-B

Write

1

Executes forced reset of bridge-Bch.

reset TSP

Read/

0

Releases FIFO reset on TSP -IC I/F side of bridge-Bch.

14

FIFO-B

Write

1

Resets FIFO on TSP-IC I/F side of bridge-Bch.

reset BRG

Read/

0

Releases FIFO reset on LINK-I/F side of bridge-Bch.

13

FIFO-B

Write

1

Resets FIFO on LINK I/F side of bridge-Bch.

Read

-

Always indicate ‘0’.

12 - 8

reserved

Write

-

Always write in ‘0’.

Read/

0

Releases forced reset of bridge-Ach.

7

reset-A

Write

1

Execute forced reset of bridge-Ach.

reset TSP

Read/

0

Releases FIFO reset on TSP -IC I/F side of bridge-Ach.

6

FIFO-A

Write

1

Resets FIFO on TSP-IC I/F of bridge-Ach.

reset BRG

Read/

0

Releases FIFO reset on LINK-I/F side of bridge-Ach.

5

FIFO-A

Write

1

Resets FIFO on LINK I/F side of bridge-Ach.

Read

-

Always indicate ‘0’.

4 - 0

Reserved

Write

-

Always write in ‘0’.

Note 1) This register is not cleared automatically.

After writing ‘1’, check the state and then write ‘0’.

Note 2) Do not set ‘1’ to this register during transmit/receive execution.

Rev.1.0 61 Fujitsu VLSI