LSI Specification

MB86617A

Address (HEX)

20

22

24

26

28

2A

2C

2E

30

32

34

36

38

3A

3C

3E

40

42

44

46

48

4A

4C

4E

WRITE

READ

 

 

Register Name

Register Name

 

 

 

 

transmit DSS packet header setting [A] (upper)

receive DSS packet header setting [A] (upper)

 

 

transmit DSS packet header setting [A] (medium)

receive DSS packet header setting [A] (medium)

 

 

transmit DSS packet header setting [A] (lower)

receive DSS packet header setting [A] (lower)

transmit DSS packet header setting [A]

receive DSS packet header setting [A]

(least significant)

(least significant)

 

 

transmit DSS packet header setting [B]

receive DSS packet header setting [B]

(most significant)

(most significant)

 

 

transmit DSS packet header setting [B] (upper)

receive DSS packet header setting [B] (upper)

 

 

transmit DSS packet header setting [B] (medium)

receive DSS packet header setting [B] (medium)

 

 

transmit DSS packet header setting [B] (lower)

receive DSS packet header setting [B] (lower)

 

 

transmit DSS packet header setting [B]

receive DSS packet header setting [B]

(least significant)

(least significant)

 

 

(reserved)

TSP status

 

 

data bridge transmit information setting 1 [A]

data bridge transmit information setting 1 [A]

 

 

data bridge transmit information setting 2 [A]

data bridge transmit information setting 2 [A]

 

 

data bridge transmit information setting 3 [B]

data bridge transmit information setting 3 [B]

 

 

data bridge transmit information setting 4 [B]

data bridge transmit information setting 4 [B]

 

 

data bridge receive information setting

data bridge receive information setting

 

 

transmit packet concatenate/split setting

transmit packet concatenate/split setting

 

 

Late packet criterion range setting [A]

Late packet criterion range setting [A]

 

 

Late packet criterion range setting [B]

Late packet criterion range setting [B]

 

 

(reserved)

receive Isochronous packet header indicate 1 [A]

 

 

(reserved)

receive Isochronous packet header indicate 2 [A]

(reserved)

receive Isochronous packet header indicate 3 [B]

 

 

(reserved)

receive Isochronous packet header indicate 4 [B]

 

 

FIFO reset

FIFO reset

 

 

(reserved)

data bridge transmit/receive status [A]

 

 

Rev.1.0

20

Fujitsu VLSI

Page 25
Image 25
Fujitsu manual LSI Specification MB86617A