LSI Specification | MB86617A |
(Note)Register and bit necessary for receiving are as follows.
Address |
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| Data |
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| DSS |
| DV | ||
00h | TSPSB=0, CPSB=0 |
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| TSEN=1, |
| DSSEN=1, | DVEN=1, |
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1Ch | Set | TV1A,TV1B,TV2A,TV2B | Set | TV1A,TV1B,TV2A,TV2B | Set | TV1A,TV1B,TV2A,TV2B | |
according to Ch received and | according to Ch received and | according to Ch received and | |||||
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| port. |
| port. |
| port. |
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40h | Set criteria for Late packet (Ach). |
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42h | Set criteria for Late packet (Bch). |
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| - | ||
3Ch | Ach received : RXSTA=1h, RXCHA(Iso channel No.) |
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Bch received : RXSTB=1h, RXCHB(Iso channel No.) |
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Rev.1.0 | 129 | Fujitsu VLSI |
