LSI Specification

MB86617A

11.2.2Self-ID Packet Receive after Transmitting Ping Packet Ping

Regardless of s-ID store bit setting in the mode- control register (refer to 7.1), the device receives self-ID packet after a ping packet transmitted and stores the data removing logical inverse section in the Asynchronous receive-FIFO.

<Flow chart from transmitting of Pig packet to receiving Self-ID packet Ping

<Host>

<Device>

START

Store ping packet to be transmitted in

Asynchronous receive buffer.

Issue Send PHY packet(21h) Issue instruction.

Read Physical packet send interrupt

(INT25)

Read Self -ID packet received interrupt

(INT29)

Store pin packet (two word) to be

transmitted in Asynchronous transmit

buffer.

Receive Transmit PHY packet (21h)instruction.

Read Asynchronous transmit buffer.

Arbitration procedure

 

Arbitration result

Lost

 

Won

 

Transmit Ping packet.

Report Physical packet send interrupt (INT25)

(assertXINT).

Store received Self-ID packet in

Asynchronous receive buffer.

recv busy=1

Report Self-ID packet received interrupt(INT29) (assertXINT)

END

Figure 11.2.2.1 Flow example of operation from Pin packet transmitting to Self -ID packet receiving

Rev.1.0

118

Fujitsu VLSI

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Image 123
Fujitsu MB86617A manual Self-ID Packet Receive after Transmitting Ping Packet Ping