LSI Specification
MB86617A
Rev.1.0 Fujitsu VLSI
88
Physical Register#05 is the register indicating availability of cable supply power standard and timeout detect of arbitration state machine.
phy/
link-
addr R/W Bit
15 Bit
14 Bit
13 Bit
12 Bit
11 Bit
10 Bit
9 Bit
8 Bit
7 Bit
6 Bit
5 Bit
4 Bit
3 Bit
2 Bit
1 Bit
0
0A h R/W - - - - - - - - Resume
_Int ISBR Loop Pwr
_fail Time
out Port_
event Enab
_accel Enab_
multi
Initial Value ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0��� ‘0’ ‘0’
<< Description of Each Bit
BIT Bit Name Action Value Function
Read - Always indicate ‘0’.
15 - 8 reserved
Write - Always write in ‘0’.
0 Does not indicate ‘1’ at Port_event bit during resume processing.
7 Resume_Int Read/
Write 1 Indicates ‘1’ at Port_event bit during resume processing.
0 Does not perform short bus reset.
6 ISBR Read/
Write 1 Performs short bus reset. Automatically clears to ‘0’ at the completion of bus
reset.
0 Indicates that port connection is in a loop.
Read
1 Indicates that port connection is in a loop.
5 Loop
Write - Clears the bit value to ‘0’ by writing in ‘1’.
0 Indicates that the cable supply power satisfies the standard.
Read
1 Indicates that the cable supply power does not satisfy the standard.
4 Pwr_fail
Write - Clears the bit value to ‘0’ by writing in ‘1’.
0 Indicates that timeout is not detected by arbitration state machine.
Read
1 Indicates that timeout is detected by arbitration state machine.
3 Timeout
Write - Clears the bit value to ‘0’ by writing in ‘1’.