LSI Specification

MB86617A

11.6. Isochronous Packet Receiving

The example of control flow for receiving Isochronous packet is shown below.

<Host>

<Device>

START

Set necessary data to registers such as

Bridg and TSPIF.

Read Receive late occurred (INT30)

interrupt.

Set value to registers such as Bridge and

TSPIF(Note).

Receive Iso packet.

Store source packet in FIFO at Bridge.

Transmit source packet to CP LSI.

Receive processed source packet from CP LSI and store it in FIFO at TSPIF.

Receive Late evaluation

Receive Late

No

 

Yes

 

Report Receive late occurred(INT30)

 

interrupt(assert XINT).

 

Discard source packet.

 

Output source packet from the TSPIF port when the value of source packet header equals to the value of cycle timer.

END

Figure 11.6 Flow example for transmitting Isochronous packet

Rev.1.0

128

Fujitsu VLSI

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Image 133
Fujitsu MB86617A manual Isochronous Packet Receiving