Fujitsu MB86617A manual Transmit CGMS/TSCH Indicate Status Register, Tsc

LSI Specification MB86617A

7.38.Transmit CGMS/TSCH Indicate Status Register

Transmit CGMS/TSCH indicate status register indicates validity of source packet input from TSP IC I/F.

AD

R/W

Bit

Bit

Bit

Bit

Bit

Bit

Bit

Bit

Bit

Bit

Bit

Bit

Bit

Bit

Bit

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

84h

R/W

-

-

-

-

-

act -

vld-T

vld-T

-

-

-

-

-

act -

vld-T

vld-T

TSC

SC

SC

TSC

SC

SC

HB

HB-2

HB-1

HA

HA-2

HA-1

Initial Value

‘0’

‘0’

‘0’

‘0’

‘0’

‘0’

‘0’

‘0’

‘0’

‘0’

‘0’

‘0’

‘0’

‘0’

‘0’

‘0’

BIT

Bit Name

Action

Value

Function

Read

-

Always indicate ‘0’.

15 - 11

reserved

Write

-

Always write in ‘0’.

0

Indicates that the packet indicated in CGMSB-1 and TSCHB-1 (82h - bit7 to 0) was

finally input from port B at TSP IC I/F.

Read

10

Act -TSCHB

1

Indicates that the packet indicated in CGMSB-2 and TSCHB-2 (82h - bit15 to 8)

was finally input from port B at TSP IC I/F.

Write

-

Clears to ‘0’ by writing “1”.

0

Indicates that the value indicated in CGMSB-2 and TSCHB-2 (82h - bit15 to 8) is

invalid.

Read

9

Vld-TSCHB-2

1

Indicates that the value indicated in CGMSB-2 and TSCHB-2 (82h - bit15 to 8) is

valid.

Write

-

Clears to ‘0’ by writing “1”.

0

Indicates that the value indicated in CGMSB -1 and

TSCHB-1 (82h -bit7 to 0) is

invalid.

Read

8

Vld-TSCHB-1

1

Indicates that the value indicated in CGMSB -1 and TSCHB-1 (82h -bit7 to 0) is

valid.

Write

-

Clears to ‘0’ by writing “1”.

Read

-

Always indicate ‘0’.

7 - 3

reserved

Write

-

Always write in ‘0’.

Rev.1.0 76 Fujitsu VLSI