LSI Specification | MB86617A | ||
10.2. Interrupt |
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| Interrupt | Interrupt Item |
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| INT1 | Loop detected |
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| INT2 | ||
| INT3 | Bus reset complete |
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| INT4 | Bus reset detected |
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| INT5 | Isochronous packet receive error |
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| INT6 | Isochronous packet receive error |
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| INT7 | Isochronous cycle too long |
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| INT8 | Bus occupancy violation |
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| INT9 | Asynchronous packet received |
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| INT10 | CPIF output header is no 47h (Transmit) |
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| INT11 | Data length short error |
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| INT12 | Data length long error |
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| INT13 | Packet format error |
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| INT14 | Header CRC error |
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| INT15 | Data CRC error |
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| INT16 | Asynchronous receive FIFO full |
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| INT17 | Asynchronous packet send |
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| INT18 | Input CGMS or TSCH changed |
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| INT19 | Acknowledge missing |
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| INT20 | Acknowledge send |
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| INT21 | Receive EMI or ODD/EVEN changed |
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| INT22 | First packet received |
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| INT23 | Cycle start packet received |
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| INT24 | Cycle start packet send |
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| INT25 | Physical packet send |
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| INT26 | Extended PHY packet received |
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| INT27 | Physical configuration packet received |
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| INT28 |
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| INT29 |
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| INT30 | Receive late occurred |
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| INT31 | Instruction abort |
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| INT32 | Transmit late occurred |
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Rev.1.0 | 108 | Fujitsu VLSI |
