
LSI Specification | MB86617A |
5.2. Isochronous Interface
This section explains the pin function of Isochronous interface.
Signal Name | I/O |
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TSVALIDA | I/O | I.O pin for indicating effective data period of TS packet (on port A) | ||
‘H’ active signal | ||||
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TSSYNCA | I/O | Input/Output pin for indicating leading data of TS packet (on port A) | ||
‘H’ active signal | ||||
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| On transmitting: sync clock input pin for input data of TS packet | ||
TSCLKA | I/O | On receiving | : sync clock output pin for output data of TS packet | |
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| (switchable either 6.144MHz or 3.072MHz) | |
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TSDA7 - 0 | I/O | I/O pin for TS packet data (on Port A) | ||
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TSCGMSA | I | Serial input pin for CGMS and TSCH information (on port A) | ||
Effective for 8 clocks since TSSYNCA input signal rising | ||||
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SELIOA | O | Output pin for switching I/O on port A | ||
Outputs ‘L’ at transmitting and ‘H’at receiving | ||||
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SELTSPA | O | Output pin for switching output device from port A | ||
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TSVALIDB | I/O | I.O pin for indicating effective data period of TS packet (on port B) | ||
‘H’ active signal | ||||
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TSSYNCB | I/O | Input/Output pin for indicating leading data of TS packet (on port B) | ||
‘H’ active signal | ||||
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| On transmitting: sync clock input pin for input data of TS packet | ||
TSCLKB | I/O | On receiving | : sync clock output pin for output data of TS packet | |
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| (switchable either 6.144MHz or 3.072MHz) | |
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TSDB7 - 0 | I/O | I/O pin for TS packet data (on port B) | ||
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TSCGMSB | I | Serial input pin for CGMS and TSCH information (on port B) | ||
Effective for 8 clocks since TSSYNCA input signal rising | ||||
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SELIOB | O | Output pin for switching I/O on port B | ||
Outputs ‘L’ at transmitting and ‘H’at receiving | ||||
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SELTSPB | O | Output pin for switching output device from port B | ||
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ICLK | I | Clock input pin from | ||
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| Output pin for signal to be allowed accessing to | ||
XILWRE | O | Asserted by completing reception of data for one source packet | ||
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| ‘L’ active signal |
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XIV | I | Input signal for enable signal of Isochronous data | ||
Output Isochronous- FIFO data to data output pin while this signal in active. | ||||
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| Switch data synchronizing with rise edge of ICLK | ||
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XFP | O | Output pin of time stamp trigger signal | ||
‘L’ active signal |
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Rev.1.0 | 14 | Fujitsu VLSI |