| LSI Specification |
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| MB86617A |
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| 8.3. Physical register #01 (read/write) |
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| Physical Register#01 is the register that set s/indicates |
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| Do not write into this register except for the case that the node is | Bus manager or Isochronous resource manager in the environment with |
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| no Bus manager. |
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| phy/ |
| Bit | Bit | Bit | Bit | Bit | Bit |
| Bit | Bit | Bit | Bit | Bit | Bit | Bit | Bit | Bit | Bit |
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| link- | R/W |
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| 15 | 14 | 13 | 12 | 11 | 10 |
| 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
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| 02 h | R/W | - | - | - | - | - | - |
| - | - | RHB | IRB |
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| Gap_count |
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| Initial Value | ‘0’ | ‘0’ | ‘0’ | ‘0’ | ‘0’ | ‘0’ |
| ‘0’ | ‘0’ | ‘0’’ | ‘0’ |
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| “3F h” |
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ョDescription of Each Bit
BIT | Bit Name | Action | Value | Function | |
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| Read | - | Always indicate ‘0’. | |
15 - 8 | reserved |
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Write | - | Always write‘0’. | |||
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| RHB | Read/ | 0 | This node does not try to be root during next bus reset. | |
7 |
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Note 1) | Write | 1 | This node tries to be root during next bus reset. | ||
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| 0 | Does not perform bus reset. | |
6 | IRB | Read/ |
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Write |
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| 1 | Performs bus reset. Automatically clears to “0” at the completion of bus reset. | ||
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| Gap_count | Read | - | Indicate current | |
5 - 0 |
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Note 2) |
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Write | - | Set | |||
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Note 1) This bit is automatically set by receiving the PHY configuration packet, too.
Note 2) This bit is automatically set by receiving the PHY configuration packet, too.
Also, this bit value returns to initial value at the second next bus reset.
Rev.1.0 | 84 | Fujitsu VLSI |